Introduction of arm_boards crate & GIC driver fixes
#915
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…eep for "1 of N" interrupts during distributor initialization
…or initialization
…m an MpidrValue" This reverts commit 5c0d9cc.
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Solid. Only two suggestions :)
kevinaboos
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* New `arm_boards` crate: per-board definitions for aarch64 builds
* The default is for QEMU's basic `virt` machine spec.
* Currently, this specifies the number of CPUs, their IDs, and
the interrupt controller configuration including one GIC
redistributor base address per core.
* The `gic` crate now uses this instead of defining its own
internal configuration values specific to QEMU.
* `multicore_bringup` now uses the list of `CpuId`s from
the selected ARM board configuration.
* The redistributor initialization routine code now enables
the dispatch of "1 of N"-distributed SPIs.
* All CPUs' redistributors are now initialized by the
bootstrap processor as part of `interrupts::init()`.
* Incorporates two fixes from #910:
* Fix a bug in `get_spi_target` & `set_spi_target` where
an atomic u32 read/write was used to manipulate a
u64 MMIO register.
* Introduce `Offset32` and `Offset64` types to distinguish
32-bit and 64-bit registers more clearly.
Co-authored-by: Kevin Boos <kevinaboos@gmail.com> d2ed7ac
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This PR brings the following changes:
arm_boardscrate: Per-board definitions for AArch64 builds - currently the number of CPUs, their IDs, and the interrupt controller configuration including one GIC redistributor base address per core (motivation for this PR)giccrate was modified to use thisinterrupts::initmulticore_bringupuses the list ofCpuIds fromarm_boards(no longer bruteforcing them)cpuwere made constvtedependency in text-terminal so thatgiccan use version0.7.2ofarrayvec(used during initialization)Two changes were directly imported from #910:
get_spi_target&set_spi_targetwhere an atomic u32 R/W was used to manipulate a u64 MMIO registerOffset32&Offset64types to distinguish 32b & 64b registersAll in all, this fixes the problems discovered via discussion on #910 (some conditions for "1 of N" distribution of SPIs were not asserted).