Fixes and improvements in GIC driver #910
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kevinaboos
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Mar 28, 2023
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Everything looks generally fine, I just made a few suggestions for minor improvements.
kevinaboos
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Mar 29, 2023
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Looks solid, just left one comment clarifying SpiDestination behavior
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* New `arm_boards` crate: per-board definitions for aarch64 builds
* The default is for QEMU's basic `virt` machine spec.
* Currently, this specifies the number of CPUs, their IDs, and
the interrupt controller configuration including one GIC
redistributor base address per core.
* The `gic` crate now uses this instead of defining its own
internal configuration values specific to QEMU.
* `multicore_bringup` now uses the list of `CpuId`s from
the selected ARM board configuration.
* The redistributor initialization routine code now enables
the dispatch of "1 of N"-distributed SPIs.
* All CPUs' redistributors are now initialized by the
bootstrap processor as part of `interrupts::init()`.
* Incorporates two fixes from #910:
* Fix a bug in `get_spi_target` & `set_spi_target` where
an atomic u32 read/write was used to manipulate a
u64 MMIO register.
* Introduce `Offset32` and `Offset64` types to distinguish
32-bit and 64-bit registers more clearly.
Co-authored-by: Kevin Boos <kevinaboos@gmail.com>
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Apr 4, 2023
* New `arm_boards` crate: per-board definitions for aarch64 builds
* The default is for QEMU's basic `virt` machine spec.
* Currently, this specifies the number of CPUs, their IDs, and
the interrupt controller configuration including one GIC
redistributor base address per core.
* The `gic` crate now uses this instead of defining its own
internal configuration values specific to QEMU.
* `multicore_bringup` now uses the list of `CpuId`s from
the selected ARM board configuration.
* The redistributor initialization routine code now enables
the dispatch of "1 of N"-distributed SPIs.
* All CPUs' redistributors are now initialized by the
bootstrap processor as part of `interrupts::init()`.
* Incorporates two fixes from #910:
* Fix a bug in `get_spi_target` & `set_spi_target` where
an atomic u32 read/write was used to manipulate a
u64 MMIO register.
* Introduce `Offset32` and `Offset64` types to distinguish
32-bit and 64-bit registers more clearly.
Co-authored-by: Kevin Boos <kevinaboos@gmail.com> d2ed7ac
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kevinaboos
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Apr 5, 2023
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left a few comments about iterator usage and type conversion implementations
kevinaboos
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Apr 6, 2023
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Small changes to the
giccrate:SpiDestination&IpiTargetCpu, which were previouslyTargetCpuTryFrom<u64>forMpidrValueto identify existing CPUs based on GIC register contents