TestABC

This is a fork version of the original Berkeley's ABC, which I use to write unit test in test folder. This probably won't be updated to the upstream since there are too many nit-picky tests, these tests are designed to be as minimum as possible to verify if the implementation align with your concept, and at the same time, help check the bug point if it exists.
These tests would be a set of really helpful tutorials for correctly using each one of the interfaces.

🔨 Build

The test framework is Googletest, it was added in the original ABC in CMake file, simple build with CMake:

mkdir build
cd build
cmake -DCMAKE_BUILD_TYPE=Debug ..
make

Tip

I suggest you enable -DCMAKE_BUILD_TYPE=Debug to get symbol table, so that you could launch lldb, gdb, etc. to debug if anything goes wrong. This is a simple example, personally I recommend you build it with Ninja, by default full load on threads. You could provide customized namespace if you want. Check workflow file for detail. Or just

cmake -G Ninja -DCMAKE_BUILD_TYPE=Debug -B build
cmake --build build

You could trigger all tests by typing

cd build
ctest --verbose --output-on-failure

Or trigger a single test by

ctest -R TEST_CASE_NAME --verbose

🧪 Test list

This section will include all the tests and test suite. Current tests:

  Test  #1: TTTest.ReadTT
  Test  #2: TTest.InvertWordTT
  Test  #3: TTest.GetWordNum
  Test  #4: TTest.GetBitTT
  Test  #5: GiaTest.CanAllocateGiaManager
  Test  #6: GiaTest.CanAddACi
  Test  #7: GiaTest.CanAddACo
  Test  #8: GiaTest.CanAddAnAndGate
  Test  #9: GiaTest.GiaCollectFanoutInfo
  Test #10: GiaSingleOperation.Gia2Aig
  Test #11: GiaSingleOperation.Aig2Gia
  Test #12: GiaSingleOperation.Gia2AigForOpt
  Test #13: GiaSingleOperation.Gia2AigForOptBack
  Test #14: GiaSingleOperation.GiaOnMapperNf9
  Test #15: GiaSingleOperation.StimeChecking
  Test #16: GiaSamples.FormChoicesWith3Samples
  Test #17: AigTest.ConstructAig
  Test #18: AigTest.StructureAnalysisAig
  Test #19: AigTest.PhasesAig
  Test #20: AigTest.NameObjAig
  Test #21: AigTest.IsMuxAig
  Test #22: AigTest.IsMuxControlAig
  Test #23: AigTest.RecITEMUXAig
  Test #24: AigTest.IsXORAig
  Test #25: AigTest.XORSelfAntiDualAig
  Test #26: AigTest.SimulationAig
  Test #27: AigTest.SimulationManualCompAig
  Test #28: AigTest.Simulation6InputsAig
  Test #29: AigTest.ReadFromFileAig
  Test #30: AigTest.DualPropertyMig
  Test #31: AigTest.CollectSingleAndAig
  Test #32: AigTest.DuplicateAig
  Test #33: AigTest.LevelTagAig
  Test #34: AigTest.ReverseLevelAig
  Test #35: AigTest.ResubAig
  Test #36: AigTest.ResubSingleNodeAig
  Test #37: AigCutTest.CutTruthVarNumAig
  Test #38: AigCutTest.CutCollect
  Test #39: AigCutTest.CutLeavesSizeCollect
  Test #40: AigCutTest.CutTreeCollect
  Test #41: AigCutTest.CutLeavesSizeCollectReal
  Test #42: AigCutTest.CutTruthSimTruth
  Test #43: GiaTest.GiaCollectFanoutInfo
  Test #44: UtilTest.UtilTruthHexPrint
  Test #45: UtilTest.UtilAddClauses

Total Tests: 45

Truth table

• TTTest, ReadTT : Show the direct interface on reading truth table into abc.

  1. Check for case.
  2. Check for ignoring leading 0x.
  3. Check for MSB(order).
  4. Check for returned number of variables.

• TTest, InvertWordTT : Get the inverted truth table of specified number of words.

• TTest, GetWordNum : Get the required number of (unsigned long)words given a specified number of variables.

• TTest, GetBitTT : Show the k(indexed) bit of a (unsigned long) word array. This interface works as follows, the k >> 6 means k divides 64, k & 63 means the modulo operation k % 64. So it first shifts to the target word and then shifts to the moduloed bit in the target word, and then extract it by & 1.

AIG

• AigTest, ConstructAig : Construct a 2 input and 1 output AIG(A single AND node).
• AigTest, StructureAnalysisAig : Analysis complemented attributes on simple AIG.
• AigTest, PhasesAig : Phases are actually initialized in AIG when you call function Abc_Obj_t * Abc_AigAnd( Abc_Aig_t * pMan, Abc_Obj_t * p0, Abc_Obj_t * p1 ). It is determined by 4 factors, the complemented attributes and regular node phases of both $p_0$ and $p_1$.

• AigTest, SimulationAig : Simulation on every condition of a 2 input AND gate. It shows a way isolated from resub to perform an exact simulation.

Caution

Do notice that the simulation process in this method use the pData in Abc_Obj_t, it is a multipurpose pointer, so be careful when mixing different kinds of interfaces, this should be avoided or add additional pointers. Eg, some choices interfaces visit pData to access candidates, which might have conflicts.

• AigTest, SimulationManualCompAig : Showcase on analyzing simulation on same structure cases with manually changed complemented attributes.
• AigTest, Simulation6InputsAig : Give a detailed analysis on a 6-input window from a case i10.aig. Show the exact simulation result in some internal nodes. Check this example to get a deep comprehension about the phases and node encoding process. The window is structured as below:

• AigTest, NameObjAig : Assign name to object in network.
• AigTest, IsMuxAig : Detecting if the current node is the root of a MUX. It is detecting a two level AIG, check the inverted attribute of the children and grand children. The tested example is shown below:

• AigTest, IsMuxControlAig : Check if the node is MUX control node type. This one uses the case in AigTest, IsMuxAig, the control node is the node $pi_0$.
• AigTest, RecITEMUXAig : Recognize a MUX and return control("if") node, "then" node, "else" node based on IFE(if-then-else) logic.

Note

The "then" and "else" nodes can be complemented.

• AigTest, IsXORAig : Check if a root node is a XOR/NXOR root node. Since the phase of the root can be changed easily, actually this interface will return true on the following 4 different cases.

Note

$(a)$ and $(b)$ are XOR and $(c)$ and $(d)$ are NXOR.

• AigTest, XORSelfAntiDualAig : Self-anti-dual case on XOR, which could also be seen as case $(a)$ to case $(b)$ from AigTest, IsXORAig.

• AigTest, LevelTagAig : Calculate level of each AND gate.

Note

CI levels are 0.

• AigTest, ReverseLevelAig : Reverse level calculation and could be used to further calculate the level slack.

Note

Abc_ObjRequiredLevel should be called after Abc_NtkStartReverseLevels, or the reverse level pNtk->vLevelsR will be NULL.

• AigTest, ResubAig : Apply resubstitution to a network. This case is from Figure 3.2.2 from paper.

• AigTest, ResubSingleNodeAig : Apply resubstitution to a single node. Case is the same as mentioned above.

• AigTest, DualPropertyMig : Self-dual function simulation on aig, using a majority gate as an example.
  The majority function is self-dual $f = xy \lor yz \lor zx$, $f^d = \overline{(\bar{x} \bar{y} \lor \bar{y} \bar{z} \lor \bar{z} \bar{x})}$, $f = f^d$.

• AigTest, CollectSingleAndAig : Collecting nodes using DFS on a single target node on AIG.

Gia

• GiaTest, GiaCollectFanoutInfo : Standard process on collecting fanout information.

Note

The interface Gia_ObjFanoutNum can not be used alone, you should call Gia_ManStaticFanoutStart and Gia_ManStaticFanoutStop before and after the fanout information collection.

• GiaSingleOperation, Gia2Aig : Gia manager transform to Aig manager.
• GiaSingleOperation, Aig2Gia : Aig manager transform to Gia manager with &cec interface verified.
• GiaSingleOperation, Gia2AigForOpt : ABC9 to ABC for optimization. There's no direct manager in old rw/rf/b, so should be transformed to Ntk level. An example of balance is given here.
• GiaSingleOperation, Gia2AigForOptBack : ABC9 to ABC for optimization. Then back to Gia manager. Omit as much high level structure as possible. An example with balance is shown here.
• GiaSingleOperation, GiaOnMapperNf9 : Simple interface on &nf mapper.
• GiaSingleOperation, StimeChecking : Give the delay and area mapping result of a mapped circuit with &nf mapper.
• GiaSamples, FormChoicesWith3Samples : Construct choice network using 3 snapshots from Gia network.

miniaig

• GiaTest, GiaCollectFanoutInfo : Test the efficiency of minaig compared to aig and gia structure. (Only has time comparison for now.)

Cuts

• AigCutTest, CutTruthVarNumAig : Testing the number of words needed to be allocated for a number of variables, node that in ABC, a word length is always considered as 32 bits.
• AigCutTest, CutCollect : Collecting cuts on a single AND node. Use the example AIG case from AigTest, Simulation6InputsAig. Note that the $n_{th}$ leaf of the cut shows the $n_{th}$ variable in simulation.
• AigCutTest, CutLeavesSizeCollect : Check the cut set difference when modifying the cut max leaf size.

Note

Trivial cut is always the first one, which only contain the node itself. You will see the check in this example.

• AigCutTest, CutTreeCollect: Collect tree cuts at a node. The case used in test is shown in the following figure.

• AigCutTest, CutLeavesSizeCollectReal : Every node type should have cuts, even only a single trivial one.
• AigCutTest, CutTruthSimTruth : Test the value of cut truth calculation, the result should be the same as Abc_ManResubSimulate's results. (However, this is not always the case, by using Abc_ManResubSimulate, phase should also be considered.)

Util

• UtilTest, UtilTruthHexPrint : Showing how to print a truth table into a hex format.

Caution

This interface has a minor issue: You should make sure that the truth unsigned Sign[] passed into the interface has absolute length equal or lower than the maximum length according to the nVars, if you pass 256 to 3 variable, you will get a 00 instead of 100. The total number of digits is decided by the nVars.

• UtilTest, UtilAddClauses : Clause interface, give example to show what it looks like, the lits are based on AIG syntax, variables are index based(roughly divided by 2, positive or negative decided by even/odd lit).