Fixing Access to the Main Memory by Cache/UART in Simulation

[Joao-Pedro-Cabral]

This commit fixes multiple bugs correlated to the use of the cache and the UART in the testbench.

The main problem is that in the current code, if when accessing the UART addresses for VMEM_W>32 (or DCACHE_LINE>32) it causes a memory exception and the code enters in infinite loop at the exception handler.

This bug happens because the UART memory address is illegal for the RAM (which makes sense), so the RAM issues an error, but in this situation the UART simulator (presents in verilator_main.cpp) must clear the error.

The official implementation only works correctly for VMEM_W=32, in the other cases the error is not cleared.

[ParkerJones567]

Due to other bugs with the caches, they have been dropped from further development efforts

[Joao-Pedro-Cabral]

But now, you don't use caches for simulation and in FPGA?
Because at least for me is very important to have a cache to do more realistic benchmarking.

Due to other bugs with the caches, they have been dropped from further development efforts

[ParkerJones567]

We are working on replacements/other cache options. Due to bugs with these cache modules, we will not be supporting them. Specifically, one issue we have found involves data corruption caused by a single cycle of reading to the wrong cache way.

Feel free to continue using them, or use other better verified memory/cache modules.