FlooNoC is a configurable, open-source Network-on-Chip (NoC) architecture designed for high-bandwidth, non-coherent multi-core clusters and AI accelerators. It addresses the bandwidth bottlenecks of traditional serialized NoCs by deploying wide physical channels that transport entire AXI4 messages (header + data) in a single flit, eliminating serialization latency.
Designed for the PULP Platform, FlooNoC decouples the low-complexity transport layer (routers) from the protocol handling (Network Interfaces), enabling high scalability. It supports end-to-end AXI4 with multiple outstanding transactions and separates traffic into parallel physical streams—isolating bulk DMA transfers from latency-sensitive control messages.
Included is FlooGen, a Python-based generation framework that produces fully connected SystemVerilog RTL, routing information and tables from a simple high-level configuration file.
The full documentation is available online.
We provide detailed guides for both the hardware IPs (FlooNoC) and the generation tool (FlooGen):
- View Hardware Docs ➔ Learn how to simulate and integrate the SystemVerilog IPs.
- View Generator Docs ➔ Learn how to install the tool and generate custom network topologies.
FlooNoC is built on five key principles to achieve high bandwidth and low latency:
-
Wide Physical Channels: Unlike traditional NoCs that serialize packets into narrow flits, FlooNoC uses wide links to send entire messages (header + data) in a single cycle. This allows endpoints to utilize their full bandwidth without being constrained by NoC frequency or serialization overhead.
-
Full AXI4 Support: The architecture fully supports AXI4+ATOPs (AXI5), handling bursts and multiple outstanding transactions efficiently. It provides end-to-end ordering and ID tracking, ensuring seamless integration with standard IP blocks.
-
Decoupled Architecture: Complexity is moved to the edges (Network Interfaces/Chimneys), keeping the routers simple and fast. This decoupling allows the network to scale to hundreds of cores without timing degradation.
-
Traffic Separation: FlooNoC can physically separate traffic classes. High-bandwidth, burst-based traffic (e.g., DMA) travels on wide links, while latency-sensitive control traffic travels on separate narrow links, preventing head-of-line blocking.
-
Modularity: The system is composed of modular building blocks—Routers, Links, and Chimneys (Network Interfaces). This modularity allows FlooGen to assemble arbitrary topologies (Mesh, Tree, Irregular) tailored to specific system requirements.
The names of the IPs are inspired by the Harry Potter universe, where the Floo Network is a magical transportation system. The Network interfaces are named after the fireplaces and chimneys used to access the Floo Network.
In use for centuries, the Floo Network, while somewhat uncomfortable, has many advantages. Firstly, unlike broomsticks, the Network can be used without fear of breaking the International Statute of Secrecy. Secondly, unlike Apparition, there is little to no danger of serious injury. Thirdly, it can be used to transport children, the elderly and the infirm."
All code checked into this repository is made available under a permissive license. All software sources are licensed under the Apache License 2.0 (see LICENSE-APACHE), and all hardware sources in the hw folder are licensed under the Solderpad Hardware License 0.51 (see LICENSE-SHL).
If you use FlooNoC in your research, please cite the following paper:
FlooNoC: A 645 Gbps/link 0.15 pJ/B/hop Open-Source NoC with Wide Physical Links and End-to-End AXI4 Parallel Multi-Stream Support
@ARTICLE{10848526,
author={Fischer, Tim and Rogenmoser, Michael and Benz, Thomas and Gürkaynak, Frank K. and Benini, Luca},
journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
title={FlooNoC: A 645-Gb/s/link 0.15-pJ/B/hop Open-Source NoC With Wide Physical Links and End-to-End AXI4 Parallel Multistream Support},
year={2025},
volume={33},
number={4},
pages={1094-1107},
keywords={Bandwidth;Very large scale integration;Data transfer;Routing;Complexity theory;Scalability;Nickel;Memory management;Engines;Europe;Advanced extensible interface (AXI);network interface (NI);network-on-chip (NoC);physical design;very large scale integration},
doi={10.1109/TVLSI.2025.3527225}}