LoopyV: A 5-Stage Pipelined RISC-V Processor

LoopyV is a SystemVerilog implementation of a RISC-V processor featuring a 5-stage pipeline architecture. This processor is designed to provide efficient instruction execution while maintaining a balance between performance and complexity.

Pipeline Stages

LoopyV implements the following pipeline stages:

1. Instruction Fetch (IF)
2. Instruction Decode (ID)
3. Execute (EX)
4. Memory (MEM)
5. Write-back (WB)

Key Features

• Full implementation of the RISC-V 32-Bit integer ISA
• Hazard detection and forwarding units for efficient pipeline operation
• Memory interface for instruction and data access

License

LoopyV is licensed under the Apache License, Version 2.0. See the LICENSE file for the full license text.

Contact

For questions or support, please open an issue in the GitHub repository or contact me.