Add visa dependent code for CRI

.

Author: matborzyszkowski

IGC/Compiler/CISACodeGen/CISABuilder.cpp

@@ -1499,6 +1499,8 @@ void CEncoder::ShflIdx4(CVariable *dst, CVariable *src0, CVariable *src1) {
   VISA_RawOpnd *dstOpnd = GetRawDestination(dst);
   VISA_PredOpnd *predOpnd = GetFlagOperand(m_encoderState.m_flag);
 
+  V(vKernel->AppendVISAShflIdx4Inst(ISA_SHFL_IDX4, predOpnd, GetAluEMask(dst), GetAluExecSize(dst), dstOpnd, src0Opnd,
+                                    src1Opnd));
 }
 // We allow H1 to be nullptr for the common case of adding 64-bit variable
 // with 32-bit imm
@@ -4363,6 +4365,9 @@ void CEncoder::InitVISABuilderOptions(TARGET_PLATFORM VISAPlatform, SIMDMode sim
   if (IGC_IS_FLAG_ENABLED(CopyA0ToDBG0)) {
     SaveOption(vISA_CopyA0ToDBG0, true);
   }
+  if (IGC_IS_FLAG_ENABLED(CopyMsg0ToDbg0)) {
+    SaveOption(vISA_CopyMsg0ToDbg0, true);
+  }
 
   if (VISAPlatform == Xe_XeHPSDV && IGC_IS_FLAG_ENABLED(DPASTokenReduction)) {
     SaveOption(vISA_EnableDPASTokenReduction, true);
@@ -4581,6 +4586,15 @@ void CEncoder::InitVISABuilderOptions(TARGET_PLATFORM VISAPlatform, SIMDMode sim
     SaveOption(vISA_EnableProgrammableOffsetsMessageBitInHeader, true);
   }
 
+  if (m_program->m_Platform->hasEfficient64bEnabled()) {
+    SaveOption(vISA_enableEfficient64b, true);
+  }
+  if (!m_program->m_Platform->supportStatefulScaleFolding()) {
+    // vISA_supportLSCImmScale has value 3 by default, which enables address
+    // offset scaling in all cases. Set value to 0 to disable UGM-scratch and
+    // SLM cases.
+    SaveOption(vISA_supportLSCImmScale, (uint32_t)0);
+  }
   if (uint32_t Val = IGC_GET_FLAG_VALUE(EnableScalarPipe)) {
     SaveOption(vISA_ScalarPipe, Val);
   }
@@ -7056,6 +7070,8 @@ void CEncoder::bdpas(CVariable *Dst, CVariable *Acc, CVariable *B, PrecisionType
       VISA_VectorOpnd *srcOpnd3 = GetSourceOperand(scalingPartsB[partIndex], noMod);
       VISA_VectorOpnd *srcOpnd4 = GetSourceOperand(scalingPartsA[partIndex], noMod);
 
+      V(vKernel->AppendVISABdpasInst(ISA_BDPAS, splitExecMask, toExecSize, dstOpnd, srcOpnd0, srcOpnd1, srcOpnd2,
+                                     srcOpnd3, srcOpnd4, src2Precision, src1Precision, systolicDepth, repeatCount));
     }
     uint32_t dstOfstBytes = m_encoderState.m_dstOperand.subVar * getGRFSize() + Dst->GetAliasOffset();
     MergePayloadToHigherSIMD(partsDst[0], partsDst[1], repeatCount, Dst, dstOfstBytes, visaNumLanes(fromExecSize));
@@ -7080,6 +7096,8 @@ void CEncoder::bdpas(CVariable *Dst, CVariable *Acc, CVariable *B, PrecisionType
     VISA_VectorOpnd *srcOpnd3 = GetSourceOperand(BScaling, noMod);
     VISA_VectorOpnd *srcOpnd4 = GetSourceOperand(AScaling, noMod);
 
+    V(vKernel->AppendVISABdpasInst(ISA_BDPAS, execMask, execSize, dstOpnd, srcOpnd0, srcOpnd1, srcOpnd2, srcOpnd3,
+                                   srcOpnd4, src2Precision, src1Precision, systolicDepth, repeatCount));
   }
 }
 
@@ -7241,6 +7259,9 @@ void CEncoder::lfsr(CVariable *dst, CVariable *src0, CVariable *src1, LFSR_FC fu
   VISA_VectorOpnd *srcOpnd0 = GetSourceOperand(src0, m_encoderState.m_srcOperand[0]);
   VISA_VectorOpnd *srcOpnd1 = GetSourceOperand(src1, m_encoderState.m_srcOperand[1]);
 
+  V(vKernel->AppendVISALfsrInst(predOpnd, GetAluEMask(dst),
+                                visaExecSize(dst->IsUniform() ? m_encoderState.m_uniformSIMDSize : simdMode), funcCtrl,
+                                dstOpnd, srcOpnd0, srcOpnd1));
 }
 
 void CEncoder::srnd(CVariable *D, CVariable *S0, CVariable *R) {
@@ -7264,6 +7285,10 @@ void CEncoder::emitDnscl(CVariable *dst, CVariable *src0, CVariable *src1, CVari
   VISA_RawOpnd *srcOpnd1 = GetRawSource(src1);
   VISA_RawOpnd *srcOpnd2 = GetRawSource(bias);
 
+  V(vKernel->AppendVISADnsclInst(
+      predOpnd, GetAluEMask(dst),
+      visaExecSize(dst->IsUniform() ? m_encoderState.m_uniformSIMDSize : m_encoderState.m_simdSize), convType, packMode,
+      roundMode, dstOpnd, srcOpnd0, srcOpnd1, srcOpnd2));
 }
 
 std::string CEncoder::GetVariableName(CVariable *var) {

IGC/Compiler/CISACodeGen/CISABuilder.hpp

@@ -338,6 +338,8 @@ class CEncoder {
   inline void USubB(CVariable *dst, CVariable *dstCarryBorrow, CVariable *src0, CVariable *src1);
   inline void IEEESqrt(CVariable *dst, CVariable *src0);
   inline void IEEEDivide(CVariable *dst, CVariable *src0, CVariable *src1);
+  inline void Tanh(CVariable *dst, CVariable *src0);
+  inline void Sigm(CVariable *dst, CVariable *src0);
   void AddPair(CVariable *Lo, CVariable *Hi, CVariable *L0, CVariable *H0, CVariable *L1, CVariable *H1 = nullptr);
   void SubPair(CVariable *Lo, CVariable *Hi, CVariable *L0, CVariable *H0, CVariable *L1, CVariable *H1);
   inline void dp4a(CVariable *dst, CVariable *src0, CVariable *src1, CVariable *src2);
@@ -897,6 +899,9 @@ inline void CEncoder::IEEESqrt(CVariable *dst, CVariable *src0) { Arithmetic(ISA
 inline void CEncoder::IEEEDivide(CVariable *dst, CVariable *src0, CVariable *src1) {
   Arithmetic(ISA_DIVM, dst, src0, src1);
 }
+inline void CEncoder::Tanh(CVariable *dst, CVariable *src0) { Arithmetic(ISA_TANH, dst, src0); }
+
+inline void CEncoder::Sigm(CVariable *dst, CVariable *src0) { Arithmetic(ISA_SIGM, dst, src0); }
 
 inline void CEncoder::dp4a(CVariable *dst, CVariable *src0, CVariable *src1, CVariable *src2) {
   Arithmetic(ISA_DP4A, dst, src0, src1, src2);

IGC/Compiler/CISACodeGen/EmitVISAPass.cpp

@@ -2299,8 +2299,10 @@ void EmitPass::EmitSimpleAlu(EOPCODE opCode, CVariable *dst, CVariable *src0, CV
     m_encoder->Inv(dst, src0);
     break;
   case llvm_tanh:
+    m_encoder->Tanh(dst, src0);
     break;
   case llvm_sigm:
+    m_encoder->Sigm(dst, src0);
     break;
   default:
     // need support
@@ -11397,6 +11399,7 @@ void EmitPass::emitStackCall(llvm::CallInst *inst) {
     IGC_ASSERT_MESSAGE(IGCLLVM::getNumArgOperands(inst) == 0, "Arguments for non-returning call are not implemented");
 
     auto *funcAddr = GetSymbol(IGCLLVM::getCalledValue(inst));
+    if (!m_currShader->m_Platform->hasEfficient64bEnabled())
       funcAddr = TruncatePointer(funcAddr);
     IGC_ASSERT_MESSAGE(funcAddr->IsUniform(), "Function address must be uniform for non-returning stack call");
     m_encoder->IndirectStackCall(nullptr, funcAddr, 0, 0);
@@ -22846,23 +22849,28 @@ void EmitPass::emitLscIntrinsicTypedLoadStatus(llvm::GenIntrinsicInst *inst) {
     CVariable *flag = nullptr;
     bool needLoop = ResourceLoopHeader(m_destination, resource, flag, label);
     CVariable *prevResult = nullptr;
+    if (!isEfficient64bEnabled && needLoop) {
       prevResult = m_currShader->GetNewVariable(numElements, ISA_TYPE_D, EALIGN_DWORD, "typedLoadStatusResult");
       CVariable *initVal = m_currShader->ImmToVariable(0, ISA_TYPE_D);
       m_encoder->SetSimdSize(SIMDMode::SIMD1);
       m_encoder->SetNoMask();
       m_encoder->Copy(m_destination, initVal);
       m_encoder->Push();
+    }
     ResourceLoopSubIteration(resource, flag, label);
     m_encoder->SetPredicate(flag);
     m_encoder->LSC_TypedReadWrite(lscOp, &resource, pU, pV, pR, pLODorSampleIdx,
                                   needLoop && prevResult ? prevResult : m_destination, eltBitSize, numElements,
                                   addrSize, writeMask.getEM(), cacheOpts);
     m_encoder->Push();
+    if (!isEfficient64bEnabled && needLoop) {
       m_encoder->SetSimdSize(SIMDMode::SIMD1);
       m_encoder->SetNoMask();
       m_encoder->Or(m_destination, prevResult, m_destination);
       m_encoder->Push();
+    }
     ResourceLoopBackEdge(needLoop, flag, label);
+    if (!isEfficient64bEnabled) {
       // Extract per-lane status from the packed status register.
       // The hardware returns a single dw register with one status bit per lane.
       // We need to broadcast the bit result into per-lane values.
@@ -22880,6 +22888,7 @@ void EmitPass::emitLscIntrinsicTypedLoadStatus(llvm::GenIntrinsicInst *inst) {
       CVariable *nonResident = m_currShader->ImmToVariable(0x0, m_destination->GetType());
       m_encoder->Select(statusFlag, m_destination, resident, nonResident);
       m_encoder->Push();
+    }
   }
   m_currShader->m_State.isMessageTargetDataCacheDataPort = true;
 }