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[Autobackout][FunctionalRegression]Revert of change: 589a708: Run LowerGEPForPrivMem pass before PreCompiledFuncImport
Change order of running passes to avoid crash.
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+24
-23
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1 file changed

+24
-23
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IGC/Compiler/CISACodeGen/ShaderCodeGen.cpp

Lines changed: 24 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -519,29 +519,6 @@ void AddLegalizationPasses(CodeGenContext &ctx, IGCPassManager &mpm, PSSignature
519519
mpm.add(new ProgramScopeConstantResolution());
520520
}
521521

522-
// Resolve the Private memory to register pass
523-
if (!isOptDisabled) {
524-
// In case of late inlining of Unmasked function allocate non
525-
// primitive Allocas after inlining is done. Otherwise there
526-
// is possibility RegAlloc cannot allocate registers for all
527-
// virtual registers. This piece of code is copied at the place
528-
// where inlining is done.
529-
if (ctx.m_instrTypes.hasNonPrimitiveAlloca &&
530-
!(IGC_IS_FLAG_ENABLED(EnableUnmaskedFunctions) && IGC_IS_FLAG_ENABLED(LateInlineUnmaskedFunc))) {
531-
mpm.add(createBreakCriticalEdgesPass());
532-
mpm.add(createAnnotateUniformAllocasPass());
533-
534-
if (IGC_IS_FLAG_DISABLED(DisablePromotePrivMem) &&
535-
!isOptDisabledForModule(ctx.getModuleMetaData(), IGCOpts::LowerGEPForPrivMemPass)) {
536-
mpm.add(createPromotePrivateArrayToReg());
537-
mpm.add(createCFGSimplificationPass());
538-
}
539-
}
540-
mpm.add(createPromoteMemoryToRegisterPass());
541-
} else {
542-
if (IGC_IS_FLAG_ENABLED(AllowMem2Reg))
543-
mpm.add(createPromoteMemoryToRegisterPass());
544-
}
545522
// This is the condition that double emulation is used.
546523
ctx.checkDPEmulationEnabled();
547524

@@ -633,6 +610,30 @@ void AddLegalizationPasses(CodeGenContext &ctx, IGCPassManager &mpm, PSSignature
633610
mpm.add(createGenericNullPtrPropagationPass());
634611
}
635612

613+
// Resolve the Private memory to register pass
614+
if (!isOptDisabled) {
615+
// In case of late inlining of Unmasked function allocate non
616+
// primitive Allocas after inlining is done. Otherwise there
617+
// is possibility RegAlloc cannot allocate registers for all
618+
// virtual registers. This piece of code is copied at the place
619+
// where inlining is done.
620+
if (ctx.m_instrTypes.hasNonPrimitiveAlloca &&
621+
!(IGC_IS_FLAG_ENABLED(EnableUnmaskedFunctions) && IGC_IS_FLAG_ENABLED(LateInlineUnmaskedFunc))) {
622+
mpm.add(createBreakCriticalEdgesPass());
623+
mpm.add(createAnnotateUniformAllocasPass());
624+
625+
if (IGC_IS_FLAG_DISABLED(DisablePromotePrivMem) &&
626+
!isOptDisabledForModule(ctx.getModuleMetaData(), IGCOpts::LowerGEPForPrivMemPass)) {
627+
mpm.add(createPromotePrivateArrayToReg());
628+
mpm.add(createCFGSimplificationPass());
629+
}
630+
}
631+
mpm.add(createPromoteMemoryToRegisterPass());
632+
} else {
633+
if (IGC_IS_FLAG_ENABLED(AllowMem2Reg))
634+
mpm.add(createPromoteMemoryToRegisterPass());
635+
}
636+
636637
if (ctx.type == ShaderType::OPENCL_SHADER || ctx.type == ShaderType::COMPUTE_SHADER) {
637638
if (IGC_IS_FLAG_ENABLED(ForceAllPrivateMemoryToSLM)) {
638639
mpm.add(new PrivateMemoryToSLM(IGC_IS_FLAG_ENABLED(EnableOptReportPrivateMemoryToSLM)));

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