Add wall clock time CSR and optimize interpreter

[edubart]

WIP. This is a experiment on #308 .

This PR stops propagating mcycle everywhere in the interpreter and allows to make a more efficient interpreter hot loop, saving 1 instruction in the Fetch+Decode+Execute (down from 12 to 11 x86_64 instructions for the FENCE instruction trace). My preliminary benchmarks says this improves about ~4% the emulator performance in fibonacci benchmark (will benchmark more later).

It also introduces a new mtime CSR, declopping machine time from machine cycle, so the machine can effectively jump its wall clock. For instance this is used during WFI instructions, so now waiting many cycles in interactive mode does not increment mcycle anymore.