rs: add access mode to sparc operand

Author: jiegec

capstone-rs/src/arch/sparc.rs

@@ -1,6 +1,6 @@
 //! Contains sparc-specific types
 
-use core::convert::From;
+use core::convert::{From, TryInto};
 use core::{cmp, fmt, slice};
 
 // XXX todo(tmfink): create rusty versions
@@ -16,13 +16,35 @@ use capstone_sys::{cs_sparc, cs_sparc_op, sparc_op_mem, sparc_op_type};
 pub use crate::arch::arch_builder::sparc::*;
 use crate::arch::DetailsArchInsn;
 use crate::instruction::{RegId, RegIdInt};
+use crate::RegAccessType;
 
 /// Contains SPARC-specific details for an instruction
 pub struct SparcInsnDetail<'a>(pub(crate) &'a cs_sparc);
 
 /// SPARC operand
+#[derive(Clone, Debug, Eq, PartialEq, Default)]
+pub struct SparcOperand {
+    /// Operand type
+    pub op_type: SparcOperandType,
+
+    /// How is this operand accessed?
+    ///
+    /// NOTE: this field is always `None` if the "full" feataure is not enabled.
+    pub access: Option<RegAccessType>,
+}
+
+impl From<&cs_sparc_op> for SparcOperand {
+    fn from(op: &cs_sparc_op) -> SparcOperand {
+        let op_type = SparcOperandType::from(op);
+        SparcOperand {
+            op_type,
+            access: op.access.try_into().ok(),
+        }
+    }
+}
+
 #[derive(Clone, Debug, Eq, PartialEq)]
-pub enum SparcOperand {
+pub enum SparcOperandType {
     /// Register
     Reg(RegId),
 
@@ -58,9 +80,9 @@ impl_PartialEq_repr_fields!(SparcInsnDetail<'a> [ 'a ];
     cc, hint, operands
 );
 
-impl Default for SparcOperand {
+impl Default for SparcOperandType {
     fn default() -> Self {
-        SparcOperand::Invalid
+        SparcOperandType::Invalid
     }
 }
 
@@ -91,21 +113,25 @@ impl_PartialEq_repr_fields!(SparcOpMem;
 
 impl cmp::Eq for SparcOpMem {}
 
-impl From<&cs_sparc_op> for SparcOperand {
-    fn from(insn: &cs_sparc_op) -> SparcOperand {
+impl From<&cs_sparc_op> for SparcOperandType {
+    fn from(insn: &cs_sparc_op) -> SparcOperandType {
         match insn.type_ {
             sparc_op_type::SPARC_OP_REG => {
-                SparcOperand::Reg(RegId(unsafe { insn.__bindgen_anon_1.reg } as RegIdInt))
+                SparcOperandType::Reg(RegId(unsafe { insn.__bindgen_anon_1.reg } as RegIdInt))
+            }
+            sparc_op_type::SPARC_OP_IMM => {
+                SparcOperandType::Imm(unsafe { insn.__bindgen_anon_1.imm })
             }
-            sparc_op_type::SPARC_OP_IMM => SparcOperand::Imm(unsafe { insn.__bindgen_anon_1.imm }),
             sparc_op_type::SPARC_OP_MEM => {
-                SparcOperand::Mem(SparcOpMem(unsafe { insn.__bindgen_anon_1.mem }))
+                SparcOperandType::Mem(SparcOpMem(unsafe { insn.__bindgen_anon_1.mem }))
             }
             sparc_op_type::SPARC_OP_MEMBAR_TAG => {
-                SparcOperand::MembarTag(unsafe { insn.__bindgen_anon_1.membar_tag })
+                SparcOperandType::MembarTag(unsafe { insn.__bindgen_anon_1.membar_tag })
+            }
+            sparc_op_type::SPARC_OP_ASI => {
+                SparcOperandType::Asi(unsafe { insn.__bindgen_anon_1.asi })
             }
-            sparc_op_type::SPARC_OP_ASI => SparcOperand::Asi(unsafe { insn.__bindgen_anon_1.asi }),
-            sparc_op_type::SPARC_OP_INVALID => SparcOperand::Invalid,
+            sparc_op_type::SPARC_OP_INVALID => SparcOperandType::Invalid,
         }
     }
 }