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rs: bump capstone to 6.0.0-Alpha4-25-g717d8b05
1 parent 202cf86 commit f8f2520

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6 files changed

+117
-52
lines changed

6 files changed

+117
-52
lines changed

‎capstone-rs/src/arch/hppa.rs‎

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -106,15 +106,10 @@ impl HppaMem {
106106
pub fn space(&self) -> RegId {
107107
RegId(self.0.space as RegIdInt)
108108
}
109-
110-
/// Base access
111-
pub fn base_access(&self) -> Option<RegAccessType> {
112-
self.0.base_access.try_into().ok()
113-
}
114109
}
115110

116111
impl_PartialEq_repr_fields!(HppaMem;
117-
base, space, base_access
112+
base, space
118113
);
119114

120115
impl cmp::Eq for HppaMem {}

‎capstone-rs/src/arch/mod.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -395,7 +395,7 @@ macro_rules! arch_info_base {
395395
)
396396
( extra_modes: )
397397
( syntax: )
398-
( both_endian: false )
398+
( both_endian: true )
399399
]
400400
[
401401
( systemz, SYSTEMZ, "arch_systemz" )

‎capstone-rs/src/arch/sparc.rs‎

Lines changed: 17 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4,18 +4,19 @@ use core::convert::From;
44
use core::{cmp, fmt, slice};
55

66
// XXX todo(tmfink): create rusty versions
7-
pub use capstone_sys::sparc_insn_group as SparcInsnGroup;
8-
pub use capstone_sys::sparc_insn as SparcInsn;
9-
pub use capstone_sys::sparc_reg as SparcReg;
7+
pub use capstone_sys::sparc_asi as SparcAsi;
108
pub use capstone_sys::sparc_cc as SparcCC;
119
pub use capstone_sys::sparc_hint as SparcHint;
10+
pub use capstone_sys::sparc_insn as SparcInsn;
11+
pub use capstone_sys::sparc_insn_group as SparcInsnGroup;
12+
pub use capstone_sys::sparc_membar_tag as SparcMembarTag;
13+
pub use capstone_sys::sparc_reg as SparcReg;
1214
use capstone_sys::{cs_sparc, cs_sparc_op, sparc_op_mem, sparc_op_type};
1315

1416
pub use crate::arch::arch_builder::sparc::*;
1517
use crate::arch::DetailsArchInsn;
1618
use crate::instruction::{RegId, RegIdInt};
1719

18-
1920
/// Contains SPARC-specific details for an instruction
2021
pub struct SparcInsnDetail<'a>(pub(crate) &'a cs_sparc);
2122

@@ -31,6 +32,12 @@ pub enum SparcOperand {
3132
/// Memory
3233
Mem(SparcOpMem),
3334

35+
/// Memory barrier tag
36+
MembarTag(SparcMembarTag),
37+
38+
/// Address space identifier
39+
Asi(SparcAsi),
40+
3441
/// Invalid
3542
Invalid,
3643
}
@@ -64,12 +71,12 @@ pub struct SparcOpMem(pub(crate) sparc_op_mem);
6471
impl SparcOpMem {
6572
/// Base register
6673
pub fn base(&self) -> RegId {
67-
RegId(RegIdInt::from(self.0.base))
74+
RegId(self.0.base as RegIdInt)
6875
}
6976

7077
/// Index register
7178
pub fn index(&self) -> RegId {
72-
RegId(RegIdInt::from(self.0.index))
79+
RegId(self.0.index as RegIdInt)
7380
}
7481

7582
/// Disp value
@@ -94,6 +101,10 @@ impl From<&cs_sparc_op> for SparcOperand {
94101
sparc_op_type::SPARC_OP_MEM => {
95102
SparcOperand::Mem(SparcOpMem(unsafe { insn.__bindgen_anon_1.mem }))
96103
}
104+
sparc_op_type::SPARC_OP_MEMBAR_TAG => {
105+
SparcOperand::MembarTag(unsafe { insn.__bindgen_anon_1.membar_tag })
106+
}
107+
sparc_op_type::SPARC_OP_ASI => SparcOperand::Asi(unsafe { insn.__bindgen_anon_1.asi }),
97108
sparc_op_type::SPARC_OP_INVALID => SparcOperand::Invalid,
98109
}
99110
}

‎capstone-rs/src/test.rs‎

Lines changed: 45 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -2091,9 +2091,7 @@ fn test_arch_hppa() {
20912091
Some(Endian::Big),
20922092
&[],
20932093
&[
2094-
// Upstream bug: access to uninitialized value
2095-
// https://github.com/capstone-engine/capstone/issues/2717
2096-
// ("ldsid", b"\x00\x20\x50\xa2"),
2094+
("ldsid", b"\x00\x20\x50\xa2"),
20972095
("mtsp", b"\x00\x01\x58\x20"),
20982096
],
20992097
);
@@ -2102,8 +2100,8 @@ fn test_arch_hppa() {
21022100
#[cfg(feature = "arch_hppa")]
21032101
#[test]
21042102
fn test_arch_hppa_detail() {
2105-
use crate::arch::hppa::HppaOperand;
2106-
use capstone_sys::hppa_reg::*;
2103+
use crate::arch::hppa::{HppaMem, HppaOperand};
2104+
use capstone_sys::{hppa_mem, hppa_reg::*};
21072105

21082106
test_arch_mode_endian_insns_detail(
21092107
&mut Capstone::new()
@@ -2117,10 +2115,6 @@ fn test_arch_hppa_detail() {
21172115
Some(Endian::Big),
21182116
&[],
21192117
&[
2120-
// Upstream bug: access to uninitialized value
2121-
// https://github.com/capstone-engine/capstone/issues/2717
2122-
// ldsid (sr1, r1), rp
2123-
/*
21242118
DII::new(
21252119
"ldsid",
21262120
b"\x00\x20\x50\xa2",
@@ -2129,17 +2123,15 @@ fn test_arch_hppa_detail() {
21292123
op_type: hppa::HppaOperandType::Mem(HppaMem(hppa_mem {
21302124
base: HPPA_REG_GR1,
21312125
space: HPPA_REG_SR1,
2132-
base_access: cs_ac_type::CS_AC_READ,
21332126
})),
2134-
access: None,
2127+
access: Some(RegAccessType::ReadOnly),
21352128
},
21362129
HppaOperand {
21372130
op_type: hppa::HppaOperandType::Reg(RegId(HPPA_REG_GR2 as RegIdInt)),
21382131
access: Some(RegAccessType::WriteOnly),
21392132
},
21402133
],
21412134
),
2142-
*/
21432135
// mtsp r1, sr1
21442136
DII::new(
21452137
"mtsp",
@@ -3373,12 +3365,13 @@ fn test_arch_sparc() {
33733365
test_arch_mode_endian_insns(
33743366
&mut Capstone::new()
33753367
.sparc()
3376-
.mode(sparc::ArchMode::Default)
3368+
.mode(sparc::ArchMode::V9)
3369+
.endian(Endian::Big)
33773370
.build()
33783371
.unwrap(),
33793372
Arch::SPARC,
3380-
Mode::Default,
3381-
None,
3373+
Mode::V9,
3374+
Some(Endian::Big),
33823375
&[],
33833376
&[
33843377
("cmp", b"\x80\xa0\x40\x02"),
@@ -3404,6 +3397,7 @@ fn test_arch_sparc() {
34043397
&mut Capstone::new()
34053398
.sparc()
34063399
.mode(sparc::ArchMode::V9)
3400+
.endian(Endian::Big)
34073401
.build()
34083402
.unwrap(),
34093403
Arch::SPARC,
@@ -3430,12 +3424,13 @@ fn test_arch_sparc_detail() {
34303424
test_arch_mode_endian_insns_detail(
34313425
&mut Capstone::new()
34323426
.sparc()
3433-
.mode(sparc::ArchMode::Default)
3427+
.mode(sparc::ArchMode::V9)
3428+
.endian(Endian::Big)
34343429
.build()
34353430
.unwrap(),
34363431
Arch::SPARC,
3437-
Mode::Default,
3438-
None,
3432+
Mode::V9,
3433+
Some(Endian::Big),
34393434
&[],
34403435
&[
34413436
// cmp %g1, %g2
@@ -3453,7 +3448,7 @@ fn test_arch_sparc_detail() {
34533448
b"\x85\xc2\x60\x08",
34543449
&[
34553450
Mem(SparcOpMem(sparc_op_mem {
3456-
base: SPARC_REG_O1 as u8,
3451+
base: SPARC_REG_O1,
34573452
index: 0,
34583453
disp: 8,
34593454
})),
@@ -3482,7 +3477,7 @@ fn test_arch_sparc_detail() {
34823477
b"\xd5\xf6\x10\x16",
34833478
&[
34843479
Mem(SparcOpMem(sparc_op_mem {
3485-
base: SPARC_REG_I0 as u8,
3480+
base: SPARC_REG_I0,
34863481
index: 0,
34873482
disp: 0,
34883483
})),
@@ -3531,7 +3526,7 @@ fn test_arch_sparc_detail() {
35313526
&[
35323527
Reg(RegId(SPARC_REG_O2 as RegIdInt)),
35333528
Mem(SparcOpMem(sparc_op_mem {
3534-
base: SPARC_REG_G1 as u8,
3529+
base: SPARC_REG_G1,
35353530
index: 0,
35363531
disp: 0,
35373532
})),
@@ -3543,8 +3538,8 @@ fn test_arch_sparc_detail() {
35433538
b"\xd4\x4e\x00\x16",
35443539
&[
35453540
Mem(SparcOpMem(sparc_op_mem {
3546-
base: SPARC_REG_I0 as u8,
3547-
index: SPARC_REG_L6 as u8,
3541+
base: SPARC_REG_I0,
3542+
index: SPARC_REG_L6,
35483543
disp: 0,
35493544
})),
35503545
Reg(RegId(SPARC_REG_O2 as RegIdInt)),
@@ -3556,6 +3551,26 @@ fn test_arch_sparc_detail() {
35563551
b"\x2a\xc2\x80\x03",
35573552
&[Reg(RegId(SPARC_REG_O2 as RegIdInt)), Imm(0x1044)],
35583553
),
3554+
// membar #LoadLoad
3555+
DII::new(
3556+
"membar",
3557+
b"\x81\x43\xe0\x01",
3558+
&[MembarTag(SparcMembarTag::SPARC_MEMBAR_TAG_LOADLOAD)],
3559+
),
3560+
// ldstuba [%i0+%l6] 4, %o2
3561+
DII::new(
3562+
"ldstuba",
3563+
b"\xd4\xee\x00\x96",
3564+
&[
3565+
Mem(SparcOpMem(sparc_op_mem {
3566+
base: SPARC_REG_I0,
3567+
index: SPARC_REG_L6,
3568+
disp: 0,
3569+
})),
3570+
Asi(SparcAsi::SPARC_ASITAG_ASI_N),
3571+
Reg(RegId(SPARC_REG_O2 as RegIdInt)),
3572+
],
3573+
),
35593574
],
35603575
);
35613576

@@ -3568,21 +3583,24 @@ fn test_arch_sparc_detail() {
35683583
&mut Capstone::new()
35693584
.sparc()
35703585
.mode(sparc::ArchMode::V9)
3586+
.endian(Endian::Big)
35713587
.build()
35723588
.unwrap(),
35733589
Arch::SPARC,
35743590
Mode::V9,
3575-
None,
3591+
Some(Endian::Big),
35763592
&[],
35773593
&[
35783594
// fcmps %f0, %f4
35793595
DII::new("fcmps", b"\x81\xa8\x0a\x24", &f0_f4),
3596+
// Upstream bug
3597+
// https://github.com/capstone-engine/capstone/issues/2749
35803598
// fstox %f0, %f4
3581-
DII::new("fstox", b"\x89\xa0\x10\x20", &f0_f4),
3599+
// DII::new("fstox", b"\x89\xa0\x10\x20", &f0_f4),
35823600
// fqtoi %f0, %f4
3583-
DII::new("fqtoi", b"\x89\xa0\x1a\x60", &f0_f4),
3601+
// DII::new("fqtoi", b"\x89\xa0\x1a\x60", &f0_f4),
35843602
// fnegq %f0, %f4
3585-
DII::new("fnegq", b"\x89\xa0\x00\xe0", &f0_f4),
3603+
// DII::new("fnegq", b"\x89\xa0\x00\xe0", &f0_f4),
35863604
],
35873605
);
35883606
}

‎capstone-sys/build.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -282,7 +282,7 @@ fn write_bindgen_bindings(
282282
.layout_tests(false) // eliminate test failures on platforms with different pointer sizes
283283
.impl_debug(true)
284284
.constified_enum_module("cs_err|cs_group_type|cs_opt_value|cs_xtensa_op_type")
285-
.bitfield_enum("cs_mode|cs_ac_type|arm_spsr_cpsr_bits")
285+
.bitfield_enum("cs_mode|cs_ac_type|arm_spsr_cpsr_bits|sparc_membar_tag")
286286
.rustified_enum(".*")
287287
.array_pointers_in_arguments(true)
288288
.no_copy("cs_insn");

‎capstone-sys/pre_generated/capstone.rs‎

Lines changed: 52 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -13852,18 +13852,59 @@ pub enum sparc_asi {
1385213852
SPARC_ASITAG_ASI_SNF_L = 139,
1385313853
SPARC_ASITAG_ASI_S_L = 137,
1385413854
}
13855-
#[repr(u32)]
13856-
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
13857-
pub enum sparc_membar_tag {
13858-
SPARC_MEMBAR_TAG_NONE = 0,
13859-
SPARC_MEMBAR_TAG_LOADLOAD = 1,
13860-
SPARC_MEMBAR_TAG_STORELOAD = 2,
13861-
SPARC_MEMBAR_TAG_LOADSTORE = 4,
13862-
SPARC_MEMBAR_TAG_STORESTORE = 8,
13863-
SPARC_MEMBAR_TAG_LOOKASIDE = 16,
13864-
SPARC_MEMBAR_TAG_MEMISSUE = 32,
13865-
SPARC_MEMBAR_TAG_SYNC = 64,
13855+
impl sparc_membar_tag {
13856+
pub const SPARC_MEMBAR_TAG_NONE: sparc_membar_tag = sparc_membar_tag(0);
13857+
}
13858+
impl sparc_membar_tag {
13859+
pub const SPARC_MEMBAR_TAG_LOADLOAD: sparc_membar_tag = sparc_membar_tag(1);
13860+
}
13861+
impl sparc_membar_tag {
13862+
pub const SPARC_MEMBAR_TAG_STORELOAD: sparc_membar_tag = sparc_membar_tag(2);
13863+
}
13864+
impl sparc_membar_tag {
13865+
pub const SPARC_MEMBAR_TAG_LOADSTORE: sparc_membar_tag = sparc_membar_tag(4);
13866+
}
13867+
impl sparc_membar_tag {
13868+
pub const SPARC_MEMBAR_TAG_STORESTORE: sparc_membar_tag = sparc_membar_tag(8);
13869+
}
13870+
impl sparc_membar_tag {
13871+
pub const SPARC_MEMBAR_TAG_LOOKASIDE: sparc_membar_tag = sparc_membar_tag(16);
13872+
}
13873+
impl sparc_membar_tag {
13874+
pub const SPARC_MEMBAR_TAG_MEMISSUE: sparc_membar_tag = sparc_membar_tag(32);
1386613875
}
13876+
impl sparc_membar_tag {
13877+
pub const SPARC_MEMBAR_TAG_SYNC: sparc_membar_tag = sparc_membar_tag(64);
13878+
}
13879+
impl ::core::ops::BitOr<sparc_membar_tag> for sparc_membar_tag {
13880+
type Output = Self;
13881+
#[inline]
13882+
fn bitor(self, other: Self) -> Self {
13883+
sparc_membar_tag(self.0 | other.0)
13884+
}
13885+
}
13886+
impl ::core::ops::BitOrAssign for sparc_membar_tag {
13887+
#[inline]
13888+
fn bitor_assign(&mut self, rhs: sparc_membar_tag) {
13889+
self.0 |= rhs.0;
13890+
}
13891+
}
13892+
impl ::core::ops::BitAnd<sparc_membar_tag> for sparc_membar_tag {
13893+
type Output = Self;
13894+
#[inline]
13895+
fn bitand(self, other: Self) -> Self {
13896+
sparc_membar_tag(self.0 & other.0)
13897+
}
13898+
}
13899+
impl ::core::ops::BitAndAssign for sparc_membar_tag {
13900+
#[inline]
13901+
fn bitand_assign(&mut self, rhs: sparc_membar_tag) {
13902+
self.0 &= rhs.0;
13903+
}
13904+
}
13905+
#[repr(transparent)]
13906+
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
13907+
pub struct sparc_membar_tag(pub libc::c_uint);
1386713908
#[doc = " Instruction's operand referring to memory\n This is associated with SPARC_OP_MEM operand type above"]
1386813909
#[repr(C)]
1386913910
#[derive(Debug, Copy, Clone)]

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