Improvements to the HDL build #103
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initial tidy up of the transmit path experiments with board_dependent configuration
updated the README
samitbasu
previously approved these changes
Sep 16, 2024
LincolnCB
previously approved these changes
Sep 16, 2024
LincolnCB
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LincolnCB
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Looks good to me. I like this default behavior, as I'm usually rebuilding just the bitstream.
This might allow us to set the properties for pins that are optimized away, as opposed to using the constraints that will create a whole bunch of warnings when trying to constrain a pin that isn't used in the project Also try and update the README a little more
twitzelbos
dismissed stale reviews from LincolnCB and samitbasu
via
c5dfb1c
added a test for reading before writing mode0
updated TODO
and to trigger transitions on an even-strobe or odd-strobe
added another test case which maybe pointless
resets - BRAMs do not support asynchronous resets and could not be inferred so long the async resets were in the design. Added a registered output to the FIFO, which is standard
this design will support...
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This PR updates the Makefile to not build device tree by default, thus allowing "lighter" installations of Vivado to build just the bitfile.
Updated the README to clarify the Makefile call and to switch to Vitis 2024.1
Updated the Makefile to checkout the 2024.1 device tree compiler from the Xilinx git.