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Merge pull request #4775 from RalfJung/spin-loop-hint
remove spin_loop hint intrinsics we no longer need
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src/shims/aarch64.rs

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@@ -19,20 +19,6 @@ pub(super) trait EvalContextExt<'tcx>: crate::MiriInterpCxExt<'tcx> {
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// Prefix should have already been checked.
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let unprefixed_name = link_name.as_str().strip_prefix("llvm.aarch64.").unwrap();
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match unprefixed_name {
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"isb" => {
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let [arg] = this.check_shim_sig_lenient(abi, CanonAbi::C, link_name, args)?;
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let arg = this.read_scalar(arg)?.to_i32()?;
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match arg {
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// SY ("full system scope")
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15 => {
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this.yield_active_thread();
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}
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_ => {
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throw_unsup_format!("unsupported llvm.aarch64.isb argument {}", arg);
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}
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}
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}
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// Used to implement the vpmaxq_u8 function.
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// Computes the maximum of adjacent pairs; the first half of the output is produced from the
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// `left` input, the second half of the output from the `right` input.

src/shims/foreign_items.rs

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Original file line numberDiff line numberDiff line change
@@ -813,22 +813,6 @@ trait EvalContextExtPriv<'tcx>: crate::MiriInterpCxExt<'tcx> {
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this, link_name, abi, args, dest,
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);
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}
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// FIXME: Move this to an `arm` submodule.
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"llvm.arm.hint" if this.tcx.sess.target.arch == Arch::Arm => {
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let [arg] = this.check_shim_sig_lenient(abi, CanonAbi::C, link_name, args)?;
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let arg = this.read_scalar(arg)?.to_i32()?;
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// Note that different arguments might have different target feature requirements.
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match arg {
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// YIELD
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1 => {
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this.expect_target_feature_for_intrinsic(link_name, "v6")?;
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this.yield_active_thread();
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}
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_ => {
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throw_unsup_format!("unsupported llvm.arm.hint argument {}", arg);
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}
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}
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}
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// Fallback to shims in submodules.
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_ => {

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