SSE Not Behaving as Expected

[bows7ring]

Hello @clementleger ,
I'm trying to run your RISC-V SSE code, using the riscv_sse_test.c module, but unfortunately, the test cases are failing.

It seems that the sse_handler is being invoked on the wrong hart. Based on my logs, it looks like the SBI is sending PMU overflow interrupts to the incorrect hart. What might be causing this issue? Could it be that I'm using the wrong version or incorrect configuration?

• Log:

• Here are the versions I'm using:
  rivos-linux/sse + opensbi-v1.6(community). (In fact, I've also tried opensbi-v1.7 and rivos-opensbi/dev/cleger/sse, but the result is the same in all cases.)

Any help would be appreciated. I noticed that this repo doesn't have an issue. If this isn't the appropriate place for such questions, please let me know.

Best regards,
Jasper