Skip to content

Commit 4f149ae

Browse files
committed
Fix signed comparision rt calls.
1 parent ecd4dd5 commit 4f149ae

File tree

8 files changed

+47
-34
lines changed

8 files changed

+47
-34
lines changed

llvm/include/llvm/IR/RuntimeLibcalls.def

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -85,6 +85,10 @@ HANDLE_LIBCALL(CMP_I16_0, nullptr)
8585
HANDLE_LIBCALL(CMP_I24_0, nullptr)
8686
HANDLE_LIBCALL(CMP_I32_0, nullptr)
8787
HANDLE_LIBCALL(CMP_I64_0, nullptr)
88+
HANDLE_LIBCALL(SCMP_I16, nullptr)
89+
HANDLE_LIBCALL(SCMP_I24, nullptr)
90+
HANDLE_LIBCALL(SCMP_I32, nullptr)
91+
HANDLE_LIBCALL(SCMP_I64, nullptr)
8892
HANDLE_LIBCALL(SCMP, nullptr)
8993
HANDLE_LIBCALL(ADD_I32, nullptr)
9094
HANDLE_LIBCALL(ADD_I32_I8, nullptr)

llvm/lib/Target/Z80/GISel/Z80CallLowering.cpp

Lines changed: 19 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -17,10 +17,11 @@
1717
#include "Z80CallingConv.h"
1818
#include "Z80ISelLowering.h"
1919
#include "Z80MachineFunctionInfo.h"
20+
#include "Z80RegisterInfo.h"
2021
#include "Z80Subtarget.h"
2122
#include "llvm/CodeGen/Analysis.h"
22-
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
2323
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
24+
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
2425
#include "llvm/Support/Debug.h"
2526
#include "llvm/Target/TargetMachine.h"
2627
using namespace llvm;
@@ -793,7 +794,7 @@ bool Z80CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
793794
const Function &F = MF.getFunction();
794795
MachineRegisterInfo &MRI = MF.getRegInfo();
795796
const DataLayout &DL = MF.getDataLayout();
796-
const Z80TargetLowering &TLI = *getTLI<Z80TargetLowering>();
797+
const auto &TLI = *getTLI<Z80TargetLowering>();
797798

798799
SmallVector<EVT, 4> SplitEVTs;
799800
ComputeValueVTs(TLI, DL, RetTy, SplitEVTs);
@@ -818,3 +819,19 @@ bool Z80CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
818819
MIRBuilder.insertInstr(MIB);
819820
return true;
820821
}
822+
823+
MachineInstrBuilder
824+
Z80CallLowering::buildSCMP(MachineIRBuilder &MIRBuilder) const {
825+
MachineFunction &MF = MIRBuilder.getMF();
826+
const auto &STI = MF.getSubtarget<Z80Subtarget>();
827+
const auto &TLI = *getTLI<Z80TargetLowering>();
828+
const Z80RegisterInfo &TRI = *STI.getRegisterInfo();
829+
bool Is24Bit = STI.is24Bit();
830+
return MIRBuilder.buildInstr(Is24Bit ? Z80::CALL24CC : Z80::CALL16CC)
831+
.addExternalSymbol(TLI.getLibcallName(RTLIB::SCMP))
832+
.addImm(Z80::COND_PE)
833+
.addDef(Z80::F, RegState::Implicit)
834+
.addUse(Z80::F, RegState::ImplicitKill)
835+
.addRegMask(
836+
TRI.getCallPreservedMask(MF, TLI.getLibcallCallingConv(RTLIB::SCMP)));
837+
}

llvm/lib/Target/Z80/GISel/Z80CallLowering.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616

1717
#include "llvm/ADT/ArrayRef.h"
1818
#include "llvm/CodeGen/GlobalISel/CallLowering.h"
19+
#include "llvm/CodeGen/MachineInstrBuilder.h"
1920

2021
namespace llvm {
2122

@@ -36,6 +37,8 @@ class Z80CallLowering : public CallLowering {
3637
ArrayRef<Register> VRegs,
3738
FunctionLoweringInfo &FLI) const override;
3839

40+
MachineInstrBuilder buildSCMP(MachineIRBuilder &MIRBuilder) const;
41+
3942
private:
4043
bool
4144
doCallerAndCalleePassArgsTheSameWay(CallLoweringInfo &Info,

llvm/lib/Target/Z80/GISel/Z80InstructionSelector.cpp

Lines changed: 5 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111
/// \todo This should be generated by TableGen.
1212
//===----------------------------------------------------------------------===//
1313

14+
#include "GISel/Z80CallLowering.h"
1415
#include "MCTargetDesc/Z80MCTargetDesc.h"
1516
#include "Z80.h"
1617
#include "Z80MachineFunctionInfo.h"
@@ -1062,7 +1063,8 @@ Z80::CondCode
10621063
Z80InstructionSelector::foldCompare(MachineInstr &I, MachineIRBuilder &MIB,
10631064
MachineRegisterInfo &MRI) const {
10641065
assert(I.getOpcode() == TargetOpcode::G_ICMP && "unexpected instruction");
1065-
const Function &F = MIB.getMF().getFunction();
1066+
MachineFunction &MF = MIB.getMF();
1067+
const Function &F = MF.getFunction();
10661068
bool OptSize = F.hasOptSize();
10671069

10681070
auto Pred = CmpInst::Predicate(I.getOperand(1).getPredicate());
@@ -1216,21 +1218,8 @@ Z80InstructionSelector::foldCompare(MachineInstr &I, MachineIRBuilder &MIB,
12161218
auto Cmp = MIB.buildInstr(Opc, {}, Ops);
12171219
if (!constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI))
12181220
return Z80::COND_INVALID;
1219-
if (IsSigned && OptSize) {
1220-
LLT s8 = LLT::scalar(8);
1221-
Type *Int8Ty = Type::getInt8Ty(F.getContext());
1222-
Register FlagsReg = MIB.buildCopy(s8, Register(Z80::F)).getReg(0);
1223-
CallLowering::ArgInfo FlagsArg(FlagsReg, Int8Ty,
1224-
CallLowering::ArgInfo::NoArgIndex);
1225-
Register SignedFlagsReg = MRI.createGenericVirtualRegister(s8);
1226-
CallLowering::ArgInfo SignedFlagsArg(SignedFlagsReg, Int8Ty,
1227-
CallLowering::ArgInfo::NoArgIndex);
1228-
createLibcall(MIB, RTLIB::SCMP, SignedFlagsArg, FlagsArg);
1229-
MIB.buildCopy(Register(Z80::F), SignedFlagsReg);
1230-
if (!RBI.constrainGenericRegister(FlagsReg, Z80::F8RegClass, MRI) ||
1231-
!RBI.constrainGenericRegister(SignedFlagsReg, Z80::F8RegClass, MRI))
1232-
return Z80::COND_INVALID;
1233-
}
1221+
if (IsSigned && OptSize)
1222+
STI.getCallLowering()->buildSCMP(MIB);
12341223
return CC;
12351224
}
12361225

llvm/lib/Target/Z80/GISel/Z80LegalizerInfo.cpp

Lines changed: 4 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -497,10 +497,10 @@ Z80LegalizerInfo::legalizeCompare(LegalizerHelper &Helper,
497497
ZeroRHS = *C == 0;
498498
switch (OpSize) {
499499
case 32:
500-
Libcall = ZeroRHS ? RTLIB::CMP_I32_0 : RTLIB::CMP_I32;
500+
Libcall = ZeroRHS ? RTLIB::CMP_I32_0 : IsSigned ? RTLIB::SCMP_I32 : RTLIB::CMP_I32;
501501
break;
502502
case 64:
503-
Libcall = ZeroRHS ? RTLIB::CMP_I64_0 : RTLIB::CMP_I64;
503+
Libcall = ZeroRHS ? RTLIB::CMP_I64_0 : IsSigned ? RTLIB::SCMP_I64 : RTLIB::CMP_I64;
504504
break;
505505
default:
506506
llvm_unreachable("Unexpected type");
@@ -530,14 +530,9 @@ Z80LegalizerInfo::legalizeCompare(LegalizerHelper &Helper,
530530
CallLowering::ArgInfo Args[2] = {{LHSReg, Ty, 0}, {RHSReg, Ty, 1}};
531531
createLibcall(MIRBuilder, Libcall, FlagsArg,
532532
makeArrayRef(Args, 2 - ZeroRHS));
533-
if (IsSigned && !ZeroRHS) {
534-
Register SignedFlagsReg = MRI.createGenericVirtualRegister(s8);
535-
CallLowering::ArgInfo SignedFlagsArg(SignedFlagsReg, Int8Ty,
536-
CallLowering::ArgInfo::NoArgIndex);
537-
createLibcall(MIRBuilder, RTLIB::SCMP, SignedFlagsArg, FlagsArg);
538-
FlagsReg = SignedFlagsReg;
539-
}
540533
MIRBuilder.buildCopy(Register(Z80::F), FlagsReg);
534+
if (IsSigned && !ZeroRHS)
535+
Subtarget.getCallLowering()->buildSCMP(MIRBuilder);
541536
} else
542537
MIRBuilder.buildInstr(Z80::RCF);
543538
MIRBuilder.buildInstr(Z80::SetCC, {DstReg}, {int64_t(CC)});

llvm/lib/Target/Z80/Z80ISelLowering.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,8 @@ Z80TargetLowering::Z80TargetLowering(const Z80TargetMachine &TM,
9292
setLibcall(RTLIB::CMP_I24_0, "_icmpzero", CallingConv::Z80_LibCall_F );
9393
setLibcall(RTLIB::CMP_I32_0, "_lcmpzero", CallingConv::Z80_LibCall_F );
9494
setLibcall(RTLIB::CMP_I64_0, "_llcmpzero",CallingConv::Z80_LibCall_F );
95+
setLibcall(RTLIB::SCMP_I32, "_lcmps", CallingConv::Z80_LibCall_F );
96+
setLibcall(RTLIB::SCMP_I64, "_llcmps", CallingConv::Z80_LibCall_F );
9597
setLibcall(RTLIB::SCMP, "_setflag", CallingConv::Z80_LibCall_F );
9698
setLibcall(RTLIB::NEG_I16, "_sneg", CallingConv::Z80_LibCall );
9799
setLibcall(RTLIB::NEG_I24, "_ineg", CallingConv::Z80_LibCall );

llvm/lib/Target/Z80/Z80Subtarget.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,6 @@
1212
//===----------------------------------------------------------------------===//
1313

1414
#include "Z80Subtarget.h"
15-
#include "GISel/Z80CallLowering.h"
1615
#include "GISel/Z80InlineAsmLowering.h"
1716
#include "GISel/Z80LegalizerInfo.h"
1817
#include "GISel/Z80RegisterBankInfo.h"

llvm/lib/Target/Z80/Z80Subtarget.h

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,10 @@
1414
#ifndef LLVM_LIB_TARGET_Z80_Z80SUBTARGET_H
1515
#define LLVM_LIB_TARGET_Z80_Z80SUBTARGET_H
1616

17+
#include "GISel/Z80CallLowering.h"
18+
#include "GISel/Z80InlineAsmLowering.h"
19+
#include "GISel/Z80LegalizerInfo.h"
20+
#include "GISel/Z80RegisterBankInfo.h"
1721
#include "Z80FrameLowering.h"
1822
#include "Z80ISelLowering.h"
1923
#include "Z80InstrInfo.h"
@@ -62,11 +66,11 @@ class Z80Subtarget final : public Z80GenSubtargetInfo {
6266
Z80FrameLowering FrameLowering;
6367

6468
/// GlobalISel related APIs.
65-
std::unique_ptr<CallLowering> CallLoweringInfo;
66-
std::unique_ptr<InlineAsmLowering> InlineAsmLoweringInfo;
69+
std::unique_ptr<Z80CallLowering> CallLoweringInfo;
70+
std::unique_ptr<Z80InlineAsmLowering> InlineAsmLoweringInfo;
6771
std::unique_ptr<InstructionSelector> InstSelector;
68-
std::unique_ptr<LegalizerInfo> Legalizer;
69-
std::unique_ptr<RegisterBankInfo> RegBankInfo;
72+
std::unique_ptr<Z80LegalizerInfo> Legalizer;
73+
std::unique_ptr<Z80RegisterBankInfo> RegBankInfo;
7074

7175
public:
7276
/// This constructor initializes the data members to match that
@@ -90,10 +94,10 @@ class Z80Subtarget final : public Z80GenSubtargetInfo {
9094
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
9195

9296
/// Methods used by Global ISel
93-
const CallLowering *getCallLowering() const override {
97+
const Z80CallLowering *getCallLowering() const override {
9498
return CallLoweringInfo.get();
9599
}
96-
const InlineAsmLowering *getInlineAsmLowering() const override {
100+
const Z80InlineAsmLowering *getInlineAsmLowering() const override {
97101
return InlineAsmLoweringInfo.get();
98102
}
99103
InstructionSelector *getInstructionSelector() const override {

0 commit comments

Comments
 (0)