Fix payload coalesing missing issue for dual-source RTW on SIMD16

fangliu2020 · sys_zuul · commit f9cc5d828355 · 2020-07-10T11:04:39.000-07:00
Change-Id: I05792fc28716ddde8f9c0f53432c02d4a5d4e3ec
diff --git a/IGC/Compiler/CISACodeGen/CoalescingEngine.cpp b/IGC/Compiler/CISACodeGen/CoalescingEngine.cpp
@@ -200,7 +200,8 @@ namespace IGC
                 {
                     GenISAIntrinsic::ID IID = intrinsic->getIntrinsicID();
                     if ((isURBWriteIntrinsic(intrinsic) && !(IGC_IS_FLAG_ENABLED(DisablePayloadCoalescing_URB))) ||
-                        (IID == GenISAIntrinsic::GenISA_RTWrite && !(IGC_IS_FLAG_ENABLED(DisablePayloadCoalescing_RT))))
+                        (IID == GenISAIntrinsic::GenISA_RTWrite && !(IGC_IS_FLAG_ENABLED(DisablePayloadCoalescing_RT))) ||
+                        (IID == GenISAIntrinsic::GenISA_RTDualBlendSource && !(IGC_IS_FLAG_ENABLED(DisablePayloadCoalescing_RT))))
                     {
                         ProcessTuple(DefMI);
                     }
@@ -1313,7 +1314,8 @@ namespace IGC
         if (isSampleInstruction(inst) ||
             isLdInstruction(inst) ||
             isURBWriteIntrinsic(inst) ||
-            IID == GenISAIntrinsic::GenISA_RTWrite)
+            IID == GenISAIntrinsic::GenISA_RTWrite ||
+            IID == GenISAIntrinsic::GenISA_RTDualBlendSource)
         {
             uint numOperands = inst->getNumOperands();
             for (uint i = 0; i < numOperands; i++)

Original file line number	Diff line number	Diff line change
`@@ -200,7 +200,8 @@ namespace IGC`
`200`	`200`	`{`
`201`	`201`	`GenISAIntrinsic::ID IID = intrinsic->getIntrinsicID();`
`202`	`202`	`if ((isURBWriteIntrinsic(intrinsic) && !(IGC_IS_FLAG_ENABLED(DisablePayloadCoalescing_URB))) \|\|`
`203`		`- (IID == GenISAIntrinsic::GenISA_RTWrite && !(IGC_IS_FLAG_ENABLED(DisablePayloadCoalescing_RT))))`
	`203`	`+ (IID == GenISAIntrinsic::GenISA_RTWrite && !(IGC_IS_FLAG_ENABLED(DisablePayloadCoalescing_RT))) \|\|`
	`204`	`+ (IID == GenISAIntrinsic::GenISA_RTDualBlendSource && !(IGC_IS_FLAG_ENABLED(DisablePayloadCoalescing_RT))))`
`204`	`205`	`{`
`205`	`206`	`ProcessTuple(DefMI);`
`206`	`207`	`}`
`@@ -1313,7 +1314,8 @@ namespace IGC`
`1313`	`1314`	`if (isSampleInstruction(inst) \|\|`
`1314`	`1315`	`isLdInstruction(inst) \|\|`
`1315`	`1316`	`isURBWriteIntrinsic(inst) \|\|`
`1316`		`- IID == GenISAIntrinsic::GenISA_RTWrite)`
	`1317`	`+ IID == GenISAIntrinsic::GenISA_RTWrite \|\|`
	`1318`	`+ IID == GenISAIntrinsic::GenISA_RTDualBlendSource)`
`1317`	`1319`	`{`
`1318`	`1320`	`uint numOperands = inst->getNumOperands();`
`1319`	`1321`	`for (uint i = 0; i < numOperands; i++)`