Synchronisation between branches

Change-Id: I716f26020732afe3c70c431bb61cec9418947635

Author: juanrod2

IGC/Compiler/CISACodeGen/DeSSA.cpp

@@ -100,7 +100,6 @@ class DeSSA : public llvm::FunctionPass {
       PHISrcArgs.clear();
       RegNodeMap.clear();
       InsEltMap.clear();
-      PrefCCMap.clear();
       AliasMap.clear();
     }
 
@@ -214,6 +213,7 @@ class DeSSA : public llvm::FunctionPass {
     llvm::Function* m_F;  // Current Function
 
     llvm::BumpPtrAllocator Allocator;
+
     // Color (label) assigned to each congruent class
     // start from 1. Make sure each Node has a different
     // color number.
@@ -241,18 +241,6 @@ class DeSSA : public llvm::FunctionPass {
     //           with a single-node in phi-union. When being isolated, they are isolated together
     llvm::MapVector<llvm::Value*, llvm::Value*> InsEltMap;
 
-    // Preferred Congruent Class Map
-    //     Assume value v0, v1, v2 are preferred to be in the same congurent class, and
-    //     assume v0 is the root (anyone could be the root), this map will be something like:
-    //         PrefCCMap[v0] = v0  // map-key == map-value: map-value is the root
-    //         PrefCCMap[v1] = v0
-    //         PrefCCMap[v2] = v0
-    // The purpose of this map is that during value isolation (main algo), if one of the preferred
-    // value is isolated, all values in the preferred CC shall be isolated as well. In another word,
-    // the preferred values will be guaranteed to stay in the same congurent class after dessa
-    // on phi's.
-    llvm::DenseMap<llvm::Value*, llvm::Value*> PrefCCMap;
-
     // Value Alias map
     //   This is used for maitaining aliases among values. It maps a value, called 'aliaser',
     //   to its 'aliasee' (denoted as alias(aliaer, aliasee). This map has the following
@@ -272,6 +260,10 @@ class DeSSA : public llvm::FunctionPass {
     //   3. Make sure DeSSA node only use aliasee.
     llvm::DenseMap<llvm::Value*, llvm::Value*> AliasMap;
 
+    // If an inst is an aliaser and no need to generate code
+    // due to aliasing, it will be added in this map.
+    llvm::DenseMap<llvm::Value*, int> NoopAliasMap;
+
     /// If there is no node for Val, create a new one.
     void addReg(llvm::Value* Val, e_alignment Align);
 
@@ -284,10 +276,18 @@ class DeSSA : public llvm::FunctionPass {
         unionRegs(RegNodeMap[Val1], RegNodeMap[Val2]);
     }
 
+    // For a value, return its representative value that is used
+    // to create dessa node, which is its aliasee's InsElt root.
+    llvm::Value* getNodeValue(llvm::Value* V) const {
+        llvm::Value* aliasee = getAliasee(V);
+        return getInsEltRoot(aliasee);
+    }
+
     llvm::Value* getInsEltRoot(llvm::Value* Val) const;
     llvm::Value* getAliasee(llvm::Value* V) const;
     bool isAliasee(llvm::Value* V) const;
     bool isAliaser(llvm::Value* V) const;
+    bool isNoopAliaser(llvm::Value* V) const;
     bool interfere(llvm::Value* V0, llvm::Value* V1);
     bool alignInterfere(e_alignment a1, e_alignment a2);
 
@@ -306,33 +306,25 @@ class DeSSA : public llvm::FunctionPass {
 
     void unionRegs(Node* N1, Node* N2);
     void CoalesceAliasInstForBasicBlock(llvm::BasicBlock *Blk);
+    int checkInsertElementAlias(
+        llvm::InsertElementInst* IEI,
+        llvm::SmallVector<llvm::Value*, 16>& AllIEIs);
+
+    // Add Val into aliasMap if it is not in the map yet.
+    // Return Val's aliasee.
     void AddAlias(llvm::Value *Val) {
-        if (AliasMap.find(Val) == AliasMap.end()) {
+        if (AliasMap.find(Val) == AliasMap.end())
             AliasMap[Val] = Val;
-        }
-    }
-    void PrefCCMapAddValue(llvm::Value *Val) {
-        if (PrefCCMap.find(Val) == PrefCCMap.end()) {
-            PrefCCMap[Val] = Val;
-        }
-    }
-
-    // Return its root if V is in a preferred CC; nullptr otherwise.
-    llvm::Value* getPrefCCRoot(llvm::Value* V) {
-        if (PrefCCMap.find(V) != PrefCCMap.end()) {
-            return PrefCCMap[V];
-        }
-        return nullptr;
     }
 
-    // If V is an inst and it is not needed (by patternmatch),
-    // return false; otherwise, return true;
-    bool isNeededIfInst(llvm::Value *V) {
+    // If V is an arg or a needed inst (by patternmatch),
+    // return true; otherwise, return false;
+    bool isArgOrNeededInst(llvm::Value *V) {
         if (llvm::Instruction* I = llvm::dyn_cast<llvm::Instruction>(V))
         {
             return CG->NeedInstruction(*I);
         }
-        return true;
+        return llvm::isa<llvm::Argument>(V);
     }
   };
 

IGC/Compiler/CISACodeGen/DeSSA.hpp

@@ -8223,7 +8223,7 @@ void EmitPass::EmitNoModifier(llvm::Instruction* inst)
     }
 
     if (IGC_IS_FLAG_ENABLED(EnableDeSSAAlias) &&
-        m_deSSA && m_deSSA->isAliaser(inst))
+        m_deSSA && m_deSSA->isNoopAliaser(inst))
     {
         return;
     }

IGC/Compiler/CISACodeGen/EmitVISAPass.cpp

@@ -980,11 +980,6 @@ inline void SetSrc0Imm32(BinInst *mybin, uint32_t value, G4_Operand* src)
         return;
     else
         mybin->SetBits(bitsSrcImm32_0,bitsSrcImm32_1,value);
-
-    if (src->isRelocImm())
-    {
-        ((G4_Reloc_Imm*)src)->setNativeOffset((unsigned int)(bitsSrcImm32_1 / 8));
-    }
 }
 
 inline void SetSrc0Imm64(BinInst *mybin, uint64_t value, G4_Operand* src)
@@ -993,11 +988,6 @@ inline void SetSrc0Imm64(BinInst *mybin, uint64_t value, G4_Operand* src)
     uint32_t high = value >> 32;
     mybin->SetBits( bitsSrcImm64_2, bitsSrcImm64_3, low );
     mybin->SetBits( bitsSrcImm64_0, bitsSrcImm64_1, high );
-
-    if (src->isRelocImm())
-    {
-        ((G4_Reloc_Imm*)src)->setNativeOffset((unsigned int)(bitsSrcImm64_3 / 8));
-    }
 }
 
 inline void EncodeSrc0RegFile(BinInst *mybin, G4_Operand *src0)
@@ -1040,11 +1030,6 @@ inline void SetSrc1Imm32(BinInst *mybin, uint32_t value, G4_Operand* src)
         return;
     else
         mybin->SetBits(bitsSrcImm32_2,bitsSrcImm32_3,value);
-
-    if (src->isRelocImm())
-    {
-        ((G4_Reloc_Imm*)src)->setNativeOffset((unsigned int)(bitsSrcImm32_3 / 8));
-    }
 }
 
 inline void EncodeSrcImmData(BinInst *mybin, G4_Operand *src)

visa/BinaryEncoding.cpp

@@ -43,27 +43,8 @@ extern int CISAdebug;
 #include "VISABuilderAPIDefinition.h"
 #include "visa_wa.h"
 
-//#define TIME_vISA_LOADING
-//#define TIME_IR_CONSTRUCTION
 class Options;
 
-class NativeRelocs
-{
-public:
-    void *operator new(size_t sz, vISA::Mem_Manager& m){ return m.alloc(sz); }
-    void addEntry(uint64_t offset, uint64_t info, int64_t addend, unsigned int nativeOffset);
-    unsigned int getNativeOffset(unsigned int cisaOffset);
-    bool isOffsetReloc(uint64_t offset, SuperRelocEntry& info);
-
-    unsigned getNumEntries() { return (uint32_t) entries.size(); }
-    SuperRelocEntry getEntry(unsigned int idx)
-    {
-        return entries[idx];
-    }
-private:
-    std::vector<SuperRelocEntry> entries;
-};
-
 class CISA_IR_Builder : public VISABuilder
 {
 public:
@@ -84,7 +65,6 @@ class CISA_IR_Builder : public VISABuilder
         m_cisaBinary = new (m_mem) CisaFramework::CisaBinary(&m_options);
         m_currentKernel = NULL;
         m_pWaTable = pWaTable;
-        nativeRelocs = NULL;
     }
 
     virtual ~CISA_IR_Builder();
@@ -769,17 +749,6 @@ class CISA_IR_Builder : public VISABuilder
     std::stringstream m_ssIsaAsm;
     std::stringstream m_ssIsaAsmHeader;
 
-    void setupNativeRelocs(unsigned int, const BasicRelocEntry*);
-    NativeRelocs* getNativeRelocs(bool createIfNULL = true)
-    {
-        if (!nativeRelocs &&
-            createIfNULL)
-        {
-            nativeRelocs = new (m_mem)NativeRelocs();
-        }
-        return nativeRelocs;
-    }
-
     void setGtpinInit(void* buf) { gtpin_init = buf; }
     void* getGtpinInit() { return gtpin_init; }
 
@@ -810,8 +779,6 @@ class CISA_IR_Builder : public VISABuilder
 
     PVISA_WA_TABLE m_pWaTable;
 
-    NativeRelocs* nativeRelocs;
-
     void* gtpin_init = nullptr;
 };
 extern _THREAD CISA_IR_Builder * pCisaBuilder;

visa/BuildCISAIR.h

@@ -74,11 +74,6 @@ CISA_IR_Builder::~CISA_IR_Builder()
         // don't call delete since vISAKernelImpl is allocated in memory pool
         kernel->~VISAKernelImpl();
     }
-
-    if (nativeRelocs)
-    {
-        nativeRelocs->~NativeRelocs();
-    }
 }
 
 void CISA_IR_Builder::InitVisaWaTable(TARGET_PLATFORM platform, Stepping step)
@@ -888,7 +883,6 @@ int CISA_IR_Builder::Compile( const char* nameInput)
 
             compilationUnits.push_back(kernel->getKernel());
 
-            kernel->setupRelocTable();
             kernel->getIRBuilder()->setIsKernel(kernel->getIsKernel());
             kernel->getIRBuilder()->setCUnitId(i);
             if( kernel->getIsKernel() == false )
@@ -975,16 +969,6 @@ int CISA_IR_Builder::Compile( const char* nameInput)
                 kernel->computeAndEmitDebugInfo(functions);
             }
 
-#ifndef DLL_MODE
-            if (m_options.getOptionCstr(vISA_RelocFilename))
-            {
-                // Emit gen reloc information to a file only in offline invocation.
-                // In DLL mode return reloc information of the kernel being
-                // compiled.
-                kernel->computeAndEmitGenRelocs();
-            }
-#endif
-
             restoreFCallState( kernel->getKernel(), savedFCallState );
 
 
@@ -1155,53 +1139,6 @@ bool CISA_IR_Builder::CISA_file_variable_decl(char * var_name,
     return true;
 }
 
-void CISA_IR_Builder::setupNativeRelocs(unsigned int numRelocs, const BasicRelocEntry* relocs)
-{
-    for (unsigned int i = 0; i < numRelocs; i++)
-    {
-        getNativeRelocs()->addEntry(relocs[i].relocOffset, relocs[i].info, relocs[i].addend, 0);
-    }
-}
-
-void NativeRelocs::addEntry(uint64_t offset, uint64_t info, int64_t addend, unsigned int nativeOffset)
-{
-    SuperRelocEntry entry;
-    entry.input.relocOffset = offset;
-    entry.input.info = info;
-    entry.input.addend = addend;
-    entry.nativeOffset = nativeOffset;
-    entries.push_back(entry);
-}
-
-bool NativeRelocs::isOffsetReloc(uint64_t offset, SuperRelocEntry& info)
-{
-    for (auto it : entries)
-    {
-        if (it.input.relocOffset == offset)
-        {
-            info = it;
-            return true;
-        }
-    }
-
-    return false;
-}
-
-unsigned int NativeRelocs::getNativeOffset(unsigned int cisaOffset)
-{
-    for (auto it : entries)
-    {
-        if (it.input.relocOffset == cisaOffset)
-        {
-            return it.nativeOffset;
-        }
-    }
-
-#define INVALID_GEN_OFFSET (0xffffffff)
-
-    return INVALID_GEN_OFFSET;
-}
-
 bool CISA_IR_Builder::CISA_addr_variable_decl(char *var_name, unsigned int var_elements, VISA_Type data_type, attr_gen_struct scope, int line_no)
 {
 

visa/BuildCISAIRImpl.cpp

@@ -408,8 +408,6 @@ class IR_Builder {
 
     bool isKernel;
     int cunit;
-    reloc_symtab* varRelocTable;
-    reloc_symtab* funcRelocTable;
     const std::vector <char*>* resolvedCalleeNames;
 
     // pre-defined declare that binds to R0 (the entire GRF)
@@ -627,10 +625,6 @@ class IR_Builder {
     int getCUnitId() { return cunit; }
     void setIsKernel( bool value ) { isKernel = value; }
     bool getIsKernel() { return isKernel; }
-    void setVarRelocTable( reloc_symtab* tab ) { varRelocTable = tab; }
-    reloc_symtab* getVarRelocTable() { return varRelocTable; }
-    void setFuncRelocTable( reloc_symtab* tab ) { funcRelocTable = tab; }
-    reloc_symtab* getFuncRelocTable() { return funcRelocTable; }
     void setResolvedCalleeNames(std::vector<char*>* nameList) { resolvedCalleeNames = nameList; }
     const std::vector<char*>* getResolvedCalleeNames() { return resolvedCalleeNames; }
     void predefinedVarRegAssignment(uint8_t inputSize);
@@ -861,7 +855,7 @@ class IR_Builder {
         Mem_Manager &m, Options *options, bool isFESP64Bits,
         FINALIZER_INFO *jitInfo = NULL, PVISA_WA_TABLE pWaTable = NULL)
         : curFile(NULL), curLine(0), curCISAOffset(-1), func_id(-1), metaData(jitInfo),
-        isKernel(false), cunit(0), varRelocTable(NULL), funcRelocTable(NULL), resolvedCalleeNames(NULL),
+        isKernel(false), cunit(0), resolvedCalleeNames(NULL),
         usesSampler(false), m_pWaTable(pWaTable), m_options(options), CanonicalRegionStride0(0, 1, 0),
         CanonicalRegionStride1(1, 1, 0), CanonicalRegionStride2(2, 1, 0), CanonicalRegionStride4(4, 1, 0),
         use64BitFEStackVars(isFESP64Bits), mem(m), phyregpool(pregs), hashtable(m), rgnpool(m), dclpool(m),
@@ -1396,10 +1390,10 @@ class IR_Builder {
     // Create immediate operand without looking up hash table. This operand
     // is a relocatable immediate type.
     //
-    G4_Reloc_Imm* createRelocImm(SuperRelocEntry& reloc, G4_Type ty)
+    G4_Reloc_Imm* createRelocImm(G4_Type ty)
     {
         G4_Reloc_Imm* newImm;
-        newImm = new (mem)G4_Reloc_Imm(reloc, ty);
+        newImm = new (mem)G4_Reloc_Imm(ty);
         return newImm;
     }