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weiyu-chenweiyu-chen
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[Autobackout][FuncReg]Revert of change: 3e5c150
(Second try) Make regOff and subregOff for srcRegRegion const. A new SrcRR should be created if offset changes. Change-Id: Ic60648b41ed82c692f45946f0bbe43665983cd92
1 parent b15d6eb commit a595a4e

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10 files changed

+113
-92
lines changed

10 files changed

+113
-92
lines changed

‎visa/BuildIR.h‎

Lines changed: 0 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -1345,48 +1345,6 @@ class IR_Builder {
13451345
return rgn;
13461346
}
13471347

1348-
G4_SrcRegRegion* createSrcWithNewRegOff(G4_SrcRegRegion* old, short newRegOff)
1349-
{
1350-
if (old->getRegAccess() == Direct)
1351-
{
1352-
return createSrcRegRegion(old->getModifier(), Direct, old->getBase(), newRegOff,
1353-
old->getSubRegOff(), old->getRegion(), old->getType(), old->getAccRegSel());
1354-
}
1355-
else
1356-
{
1357-
return createIndirectSrc(old->getModifier(), old->getBase(), newRegOff, old->getSubRegOff(),
1358-
old->getRegion(), old->getType(), old->getAddrImm());
1359-
}
1360-
}
1361-
1362-
G4_SrcRegRegion* createSrcWithNewSubRegOff(G4_SrcRegRegion* old, short newSubRegOff)
1363-
{
1364-
if (old->getRegAccess() == Direct)
1365-
{
1366-
return createSrcRegRegion(old->getModifier(), old->getRegAccess(), old->getBase(), old->getRegOff(),
1367-
newSubRegOff, old->getRegion(), old->getType(), old->getAccRegSel());
1368-
}
1369-
else
1370-
{
1371-
return createIndirectSrc(old->getModifier(), old->getBase(), old->getRegOff(), newSubRegOff,
1372-
old->getRegion(), old->getType(), old->getAddrImm());
1373-
}
1374-
}
1375-
1376-
G4_SrcRegRegion* createSrcWithNewBase(G4_SrcRegRegion* old, G4_VarBase* newBase)
1377-
{
1378-
if (old->getRegAccess() == Direct)
1379-
{
1380-
return createSrcRegRegion(old->getModifier(), Direct, newBase, old->getRegOff(),
1381-
old->getSubRegOff(), old->getRegion(), old->getType(), old->getAccRegSel());
1382-
}
1383-
else
1384-
{
1385-
return createIndirectSrc(old->getModifier(), newBase, old->getRegOff(), old->getSubRegOff(),
1386-
old->getRegion(), old->getType(), old->getAddrImm());
1387-
}
1388-
}
1389-
13901348
G4_SrcRegRegion* createIndirectSrc(G4_SrcModifier m,
13911349
G4_VarBase* b,
13921350
short roff,

‎visa/Gen4_IR.cpp‎

Lines changed: 28 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3957,9 +3957,12 @@ void G4_Areg::emit(std::ostream& output, bool symbolreg)
39573957
// initial all values idential to rgn's
39583958
//
39593959
G4_SrcRegRegion::G4_SrcRegRegion(G4_SrcRegRegion &rgn)
3960-
: G4_Operand(G4_Operand::srcRegRegion), acc(rgn.acc), regOff(rgn.regOff), subRegOff(rgn.subRegOff)
3960+
: G4_Operand(G4_Operand::srcRegRegion)
39613961
{
39623962
base = rgn.base;
3963+
acc = rgn.acc;
3964+
regOff = rgn.regOff;
3965+
subRegOff = rgn.subRegOff;
39633966
mod = rgn.mod;
39643967
immAddrOff = rgn.immAddrOff;
39653968
desc = rgn.desc;
@@ -3970,7 +3973,6 @@ G4_SrcRegRegion::G4_SrcRegRegion(G4_SrcRegRegion &rgn)
39703973
*sw1 = *sw2;
39713974
accRegSel = rgn.accRegSel;
39723975

3973-
// FIXME: it's rather suspicious that we are copying internal fields this way
39743976
bitVec[0] = rgn.bitVec[0];
39753977
bitVec[1] = rgn.bitVec[1];
39763978

@@ -3980,7 +3982,31 @@ G4_SrcRegRegion::G4_SrcRegRegion(G4_SrcRegRegion &rgn)
39803982
byteOffset = rgn.byteOffset;
39813983
rightBoundSet = rgn.rightBoundSet;
39823984
}
3985+
//
3986+
// Initialize all values idential to rgn's, except for the base operand.
3987+
// Caller is responsible for allocating base operand and making sure it doesn't
3988+
// mess up the operands' hash table.
3989+
//
3990+
G4_SrcRegRegion::G4_SrcRegRegion(G4_SrcRegRegion &rgn, G4_VarBase *new_base)
3991+
: G4_Operand(G4_Operand::srcRegRegion)
3992+
{
3993+
acc = rgn.acc;
3994+
regOff = rgn.regOff;
3995+
subRegOff = rgn.subRegOff;
3996+
mod = rgn.mod;
3997+
immAddrOff = rgn.immAddrOff;
3998+
desc = rgn.desc;
3999+
type = rgn.type;
4000+
// copy swizzle value
4001+
char *sw1 = swizzle, *sw2 = rgn.swizzle;
4002+
while (*sw2) *sw1++ = *sw2++;
4003+
*sw1 = *sw2;
4004+
4005+
base = new_base;
39834006

4007+
computeLeftBound();
4008+
rightBoundSet = false;
4009+
}
39844010
//
39854011
// return true if rng and this have the same reg region
39864012
//

‎visa/Gen4_IR.hpp‎

Lines changed: 30 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2826,10 +2826,10 @@ namespace vISA
28262826
char swizzle[max_swizzle]; // this should only be set in binary encoding
28272827

28282828
G4_SrcModifier mod;
2829-
const G4_RegAccess acc;
2829+
G4_RegAccess acc; // direct, indirect GenReg or indirect MsgReg
28302830
const RegionDesc *desc;
2831-
const short regOff; // base+regOff is the starting register of the region
2832-
const short subRegOff; // sub reg offset related to the regVar in "base"
2831+
short regOff; // base+regOff is the starting register of the region
2832+
short subRegOff; // sub reg offset related to the regVar in "base"
28332833
short immAddrOff; // imm addr offset
28342834

28352835
G4_SrcRegRegion(G4_SrcModifier m,
@@ -2851,10 +2851,9 @@ namespace vISA
28512851
right_bound = 0;
28522852
}
28532853

2854-
void setSrcBitVec(uint8_t exec_size);
2855-
28562854
public:
28572855
G4_SrcRegRegion(G4_SrcRegRegion& rgn);
2856+
G4_SrcRegRegion(G4_SrcRegRegion& rgn, G4_VarBase* new_base);
28582857
void *operator new(size_t sz, Mem_Manager& m) {return m.alloc(sz);}
28592858

28602859
bool operator==(const G4_SrcRegRegion &other)
@@ -2870,8 +2869,28 @@ namespace vISA
28702869
}
28712870

28722871
void computeLeftBound();
2872+
void setSrcBitVec(uint8_t exec_size);
28732873
short getRegOff() const { return regOff; }
28742874
short getSubRegOff() const { return subRegOff; }
2875+
void setSubRegOff(short off)
2876+
{
2877+
if (subRegOff != off)
2878+
{
2879+
subRegOff = off;
2880+
computeLeftBound();
2881+
unsetRightBound();
2882+
}
2883+
}
2884+
2885+
void setRegOff(short off)
2886+
{
2887+
if (regOff != off)
2888+
{
2889+
regOff = off;
2890+
unsetRightBound();
2891+
computeLeftBound();
2892+
}
2893+
}
28752894

28762895
const char* getSwizzle() const { return swizzle; }
28772896
G4_SrcModifier getModifier() const { return mod; }
@@ -2925,7 +2944,6 @@ namespace vISA
29252944

29262945
void setType(G4_Type ty)
29272946
{
2928-
// FIXME: we should forbid setType() where ty has a different size than old type
29292947
bool recomputeLeftBound = false;
29302948

29312949
if (G4_Type_Table[type].byteSize != G4_Type_Table[ty].byteSize)
@@ -2939,6 +2957,12 @@ namespace vISA
29392957
if (recomputeLeftBound)
29402958
{
29412959
computeLeftBound();
2960+
2961+
if (getInst())
2962+
{
2963+
getInst()->computeLeftBoundForImplAcc((G4_Operand*) getInst()->getImplAccDst());
2964+
getInst()->computeLeftBoundForImplAcc(getInst()->getImplAccSrc());
2965+
}
29422966
}
29432967
}
29442968

‎visa/GraphColor.cpp‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7896,8 +7896,8 @@ void VarSplit::insertMovesToTemp(IR_Builder& builder, G4_Declare* oldDcl, G4_Ope
78967896
{
78977897
unsigned maskFlag = (inst->getOption() & 0xFFF010C);
78987898
G4_DstRegRegion* dst = builder.Create_Dst_Opnd_From_Dcl(subDcl, 1);
7899-
auto src = builder.createSrcRegRegion(Mod_src_undef, Direct, oldDcl->getRegVar(),
7900-
(gra.getSubOffset(subDcl)) / G4_GRF_REG_NBYTES, 0, builder.getRegionStride1(), oldDcl->getElemType());
7899+
G4_SrcRegRegion* src = builder.Create_Src_Opnd_From_Dcl(oldDcl, builder.getRegionStride1());
7900+
src->setRegOff((gra.getSubOffset(subDcl)) / G4_GRF_REG_NBYTES);
79017901
G4_INST* splitInst = builder.createMov((uint8_t)subDcl->getTotalElems(), dst, src, maskFlag, false);
79027902
bb->insert(iter, splitInst);
79037903
}
@@ -7956,8 +7956,10 @@ void VarSplit::insertMovesFromTemp(G4_Kernel& kernel, G4_Declare* oldDcl, int in
79567956
bb->insert(instIter, movInst);
79577957
}
79587958
}
7959-
auto newSrc = kernel.fg.builder->createSrcRegRegion(oldSrc->getModifier(), Direct, newDcl->getRegVar(),
7960-
0, oldSrc->getSubRegOff(), oldSrc->getRegion(), newDcl->getElemType());
7959+
G4_SrcRegRegion* newSrc = kernel.fg.builder->Create_Src_Opnd_From_Dcl(newDcl, oldSrc->getRegion());
7960+
newSrc->setRegOff(0);
7961+
newSrc->setSubRegOff(oldSrc->getSubRegOff());
7962+
newSrc->setModifier(oldSrc->getModifier());
79617963
inst->setSrc(newSrc, pos);
79627964
}
79637965
else

‎visa/HWConformity.cpp‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6858,8 +6858,10 @@ static void expandPlaneMacro(IR_Builder& builder, INST_LIST_ITER it, G4_BB* bb,
68586858
G4_SrcRegRegion* srcR = builder.createSrcRegRegion(src0->getModifier(), Direct, src0->getBase(),
68596859
src0->getRegOff(), src0->getSubRegOff() + 3, builder.getRegionScalar(), src0->getType());
68606860

6861-
auto u = builder.createSrcWithNewRegOff(src1, src1->getRegOff() + (secondHalf ? 2 : 0));
6862-
auto v = builder.createSrcWithNewRegOff(src1, src1->getRegOff() + (secondHalf ? 3 : 1));
6861+
G4_SrcRegRegion* u = builder.duplicateOperand(src1);
6862+
u->setRegOff(u->getRegOff() + (secondHalf ? 2 : 0));
6863+
G4_SrcRegRegion* v = builder.duplicateOperand(src1);
6864+
v->setRegOff(v->getRegOff() + (secondHalf ? 3 : 1));
68636865

68646866
uint32_t options = inst->getOption();
68656867
if (inst->getExecSize() == 16)

‎visa/LocalRA.cpp‎

Lines changed: 14 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2812,7 +2812,8 @@ bool LinearScan::allocateRegs(LocalLiveRange* lr, G4_BB* bb, IR_Builder& builder
28122812
if (totalElems == 32)
28132813
{
28142814
G4_DstRegRegion* dst = builder.createDstRegRegion(Direct, splitDcl->getRegVar(), 2, 0, 1, oldDcl->getElemType());
2815-
auto src = builder.createSrcRegRegion(Mod_src_undef, Direct, oldDcl->getRegVar(), 2, 0, builder.getRegionStride1(), oldDcl->getElemType());
2815+
G4_SrcRegRegion* src = builder.Create_Src_Opnd_From_Dcl(oldDcl, builder.getRegionStride1());
2816+
src->setRegOff(2);
28162817
G4_INST* splitInst2 = builder.createMov(16, dst, src, InstOpt_WriteEnable, false);
28172818
bb->insert(iter, splitInst2);
28182819
}
@@ -2842,7 +2843,8 @@ bool LinearScan::allocateRegs(LocalLiveRange* lr, G4_BB* bb, IR_Builder& builder
28422843
if (totalElems == 32)
28432844
{
28442845
G4_DstRegRegion* dst = builder.createDstRegRegion(Direct, newDcl->getRegVar(), 2, 0, 1, splitDcl->getElemType());
2845-
auto src = builder.createSrcRegRegion(Mod_src_undef, Direct, splitDcl->getRegVar(), 2, 0, builder.getRegionStride1(), splitDcl->getElemType());
2846+
G4_SrcRegRegion* src = builder.Create_Src_Opnd_From_Dcl(splitDcl, builder.getRegionStride1());
2847+
src->setRegOff(2);
28462848
G4_INST* movInst2 = builder.createMov(16, dst, src, InstOpt_WriteEnable, false);
28472849
bb->insert(iter, movInst2);
28482850
}
@@ -2859,8 +2861,11 @@ bool LinearScan::allocateRegs(LocalLiveRange* lr, G4_BB* bb, IR_Builder& builder
28592861
newSrcDcl->copyAlign(oldSrcDcl);
28602862
newSrcDcl->setAliasDeclare(aliasOldSrcDcl, oldSrcDcl->getAliasOffset());
28612863
}
2862-
auto newSrc = builder.createSrcRegRegion(oldSrc->getModifier(), Direct, newSrcDcl->getRegVar(),
2863-
oldSrc->getRegOff(), oldSrc->getSubRegOff(), oldSrc->getRegion(), oldSrc->getType());
2864+
G4_SrcRegRegion* newSrc = builder.Create_Src_Opnd_From_Dcl(newSrcDcl, oldSrc->getRegion());
2865+
newSrc->setRegOff(oldSrc->getRegOff());
2866+
newSrc->setSubRegOff(oldSrc->getSubRegOff());
2867+
newSrc->setModifier(oldSrc->getModifier());
2868+
newSrc->setType(oldSrc->getType());
28642869
useInst->setSrc(newSrc, pos);
28652870
while (aliasOldSrcDcl && aliasOldSrcDcl != oldDcl)
28662871
{
@@ -2889,8 +2894,11 @@ bool LinearScan::allocateRegs(LocalLiveRange* lr, G4_BB* bb, IR_Builder& builder
28892894
newSrcDcl->copyAlign(oldSrcDcl);
28902895
newSrcDcl->setAliasDeclare(aliasOldSrcDcl, oldSrcDcl->getAliasOffset());
28912896
}
2892-
auto newSrc = builder.createSrcRegRegion(oldSrc->getModifier(), Direct, newSrcDcl->getRegVar(),
2893-
oldSrc->getRegOff(), oldSrc->getSubRegOff(), oldSrc->getRegion(), oldSrc->getType());;
2897+
G4_SrcRegRegion* newSrc = builder.Create_Src_Opnd_From_Dcl(newSrcDcl, oldSrc->getRegion());
2898+
newSrc->setRegOff(oldSrc->getRegOff());
2899+
newSrc->setSubRegOff(oldSrc->getSubRegOff());
2900+
newSrc->setModifier(oldSrc->getModifier());
2901+
newSrc->setType(oldSrc->getType());
28942902
useInst->setSrc(newSrc, pos);
28952903
while (aliasOldSrcDcl && aliasOldSrcDcl != oldDcl)
28962904
{

‎visa/Optimizer.cpp‎

Lines changed: 11 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -3351,9 +3351,9 @@ void Optimizer::cselPeepHoleOpt()
33513351
useInst->setCondMod(builder.duplicateOperand(mod));
33523352
useInst->setPredicate(NULL);
33533353

3354-
G4_SrcRegRegion* opnd2 = useInst->getSrc(2)->asSrcRegRegion();
3354+
G4_SrcRegRegion * opnd2 = useInst->getSrc(2)->asSrcRegRegion();
33553355

3356-
if (!opnd2->isScalar() && inst->getExecSize() > useInst->getExecSize())
3356+
if(!opnd2->isScalar() && inst->getExecSize() > useInst->getExecSize())
33573357
{
33583358
//earlier check establishes that useInst mask is equivalent or subset
33593359
//sel instruction
@@ -3362,18 +3362,16 @@ void Optimizer::cselPeepHoleOpt()
33623362
cmp (16)
33633363
sel (8)
33643364
*/
3365-
if (useInst->getMaskOffset() != inst->getMaskOffset())
3365+
if(useInst->getMaskOffset() != inst->getMaskOffset())
33663366
{
3367-
//check elsewhere guarantees this is float.
3367+
//check elsewhere gurantees this is float.
33683368
G4_Type type = opnd2->getType();
3369-
unsigned short typeSize = (unsigned short)G4_Type_Table[type].byteSize;
3370-
unsigned offset = opnd2->getRegOff() * G4_GRF_REG_NBYTES + opnd2->getSubRegOff() * typeSize;
3369+
unsigned short typeSize = (unsigned short) G4_Type_Table[type].byteSize;
3370+
unsigned offset = opnd2->getRegOff()* G4_GRF_REG_NBYTES + opnd2->getSubRegOff()*typeSize;
33713371
offset += useInst->getExecSize() * src0Stride * typeSize;
33723372

3373-
auto newSrc2 = builder.createSrcRegRegion(opnd2->getModifier(), Direct, opnd2->getBase(),
3374-
offset / G4_GRF_REG_NBYTES, (offset % G4_GRF_REG_NBYTES) / typeSize, opnd2->getRegion(),
3375-
opnd2->getType());
3376-
useInst->setSrc(newSrc2, 2);
3373+
opnd2->setRegOff(offset % G4_GRF_REG_NBYTES);
3374+
opnd2->setSubRegOff(offset / G4_GRF_REG_NBYTES);
33773375
}
33783376
}
33793377
//
@@ -3459,14 +3457,12 @@ static void expandPseudoLogic(IR_Builder& builder,
34593457
// we have to use the upper flag bits (.1) instead
34603458
MUST_BE_TRUE(inst->getSrc(0)->isSrcRegRegion() && inst->getSrc(0)->isFlag(),
34613459
"expect src0 to be flag");
3462-
auto newSrc0 = builder.createSrcWithNewSubRegOff(inst->getSrc(0)->asSrcRegRegion(), 1);
3463-
inst->setSrc(newSrc0, 0);
3460+
inst->getSrc(0)->asSrcRegRegion()->setSubRegOff(1);
34643461
if (inst->getSrc(1) != nullptr)
34653462
{
34663463
MUST_BE_TRUE(inst->getSrc(1)->isSrcRegRegion() && inst->getSrc(1)->isFlag(),
34673464
"expect src1 to be flag");
3468-
auto newSrc1 = builder.createSrcWithNewSubRegOff(inst->getSrc(1)->asSrcRegRegion(), 1);
3469-
inst->setSrc(newSrc1, 1);
3465+
inst->getSrc(1)->asSrcRegRegion()->setSubRegOff(1);
34703466
}
34713467
inst->getDst()->setSubRegOff(1);
34723468
}
@@ -4084,8 +4080,7 @@ bool Optimizer::foldPseudoNot(G4_BB* bb, INST_LIST_ITER& iter)
40844080
{
40854081
// Fold upper bits
40864082
assert(notInst->getExecSize() == 16);
4087-
origUse = builder.createSrcWithNewSubRegOff(origUse, 1);
4088-
notInst->setSrc(origUse, 0);
4083+
origUse->setSubRegOff(1);
40894084
}
40904085
for (auto uses = notInst->use_begin(), uend = notInst->use_end(); uses != uend; ++uses)
40914086
{

‎visa/SpillCode.cpp‎

Lines changed: 14 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -371,7 +371,8 @@ void SpillManager::replaceSpilledSrc(G4_BB* bb,
371371
}
372372
else
373373
{
374-
s = builder.createSrcWithNewBase(ss, spDcl->getRegVar()); // using spDcl as new base
374+
G4_SrcRegRegion rgn(*ss, spDcl->getRegVar()); // using spDcl as new base
375+
s = builder.createSrcRegRegion(rgn);
375376
}
376377
inst->setSrc(s,i);
377378
}
@@ -388,27 +389,27 @@ void SpillManager::replaceSpilledSrc(G4_BB* bb,
388389

389390
uint16_t num_reg = 1;
390391
//if access is VxH copy number of addresses based on execution size of instruction
391-
if (ss->getRegion()->isRegionWH())
392+
if(ss->getRegion()->isRegionWH())
392393
{
393394
num_reg = inst->getExecSize();
394395
}
395396

396397
G4_Declare* tmpDcl = NULL;
397398
bool match_found = false;
398399

399-
for (unsigned int j = 0; j < i; j++)
400+
for(unsigned int j = 0; j < i; j++)
400401
{
401-
G4_SrcRegRegion* analyzed_src = (G4_SrcRegRegion*)operands_analyzed[j];
402-
if (analyzed_src != NULL &&
402+
G4_SrcRegRegion* analyzed_src = (G4_SrcRegRegion*) operands_analyzed[j];
403+
if( analyzed_src != NULL &&
403404
analyzed_src->getBase()->asRegVar()->getDeclare() == ss->getBase()->asRegVar()->getDeclare() &&
404-
analyzed_src->getSubRegOff() == ss->getSubRegOff())
405+
analyzed_src->getSubRegOff() == ss->getSubRegOff() )
405406
{
406407
tmpDcl = declares_created[j];
407408
match_found = true;
408409
}
409410
}
410411

411-
if (!match_found)
412+
if( !match_found )
412413
{
413414
tmpDcl = createNewTempAddrDeclare(spDcl, num_reg);
414415
operands_analyzed[i] = ss;
@@ -423,11 +424,13 @@ void SpillManager::replaceSpilledSrc(G4_BB* bb,
423424
tmpDcl->getNumElems(), getGenxPlatform() >= GENX_CNL ? false : true);
424425
}
425426

426-
auto s = builder.createSrcWithNewBase(ss, tmpDcl->getRegVar()); // using tmpDcl as new base
427-
inst->setSrc(s, i);
428-
if (!match_found)
427+
G4_SrcRegRegion rgn(*ss, tmpDcl->getRegVar()); // using tmpDcl as new base
428+
G4_SrcRegRegion* s = builder.createSrcRegRegion(rgn);
429+
s->setSubRegOff(0);
430+
inst->setSrc(s,i);
431+
if( !match_found )
429432
{
430-
pointsToAnalysis.insertAndMergeFilledAddr(ss->getBase()->asRegVar(), tmpDcl->getRegVar());
433+
pointsToAnalysis.insertAndMergeFilledAddr( ss->getBase()->asRegVar(), tmpDcl->getRegVar() );
431434
}
432435
}
433436
else

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