Add option to skip memory fence commit.

Author: weiyu-chen

visa/Optimizer.cpp

@@ -6875,16 +6875,6 @@ bool Optimizer::foldPseudoAndOr(G4_BB* bb, INST_LIST_ITER& ii)
 
 
     // some workaround for HW restrictions.  We apply them here so as not to affect optimizations, RA, and scheduling
-    // [DevBDW:A]: A goto instruction must not be followed by any instruction requiring register indirect access on source operands.
-    // [DevBDW:A]: A join instruction must not be followed by any instruction requiring register indirect access on source operands.
-    // [DevBDW]: A POW/FDIV operation must not be followed by an instruction that requires two destination registers.
-    // For BDW A-stepping, we need a WA to prevent the following instructions:
-    // Send r10  (read from data port to r10)
-    // Send null r10 (write dataport from r10)
-    // Insert a dummy mov from r10
-    // [BDW+]: call/return's execution size must be set to 16/32 so that the emask will be passed correctly to the callee
-    // [BDW,CHV,SKL]: A call instruction must be followed by an instruction that supports Switch.
-    //                When call takes a jump, the first instruction must have a Switch.
     void Optimizer::HWWorkaround()
     {
         // Ensure the first instruction of a stack function has switch option.
@@ -6908,7 +6898,7 @@ bool Optimizer::foldPseudoAndOr(G4_BB* bb, INST_LIST_ITER& ii)
                 G4_INST *inst = *ii;
 
                 G4_InstSend* sendInst = inst->asSendInst();
-                if (sendInst && sendInst->isFence())
+                if (sendInst && sendInst->isFence() && !builder.getOption(vISA_skipFenceCommit))
                 {
                     // ToDo: replace with fence.wait intrinsic so we could hide fence latency by scheduling them apart
                     if (sendInst->getMsgDesc()->ResponseLength() > 0)

visa/include/VISAOptions.def

@@ -191,6 +191,7 @@ DEF_VISA_OPTION(vISA_SWSBStitch,      ET_BOOL,  "-SWSBStitch",    UNUSED, false)
 DEF_VISA_OPTION(vISA_UseOldSubRoutineAugIntf,    ET_BOOL, (IGC_MANGLE("-useOldSubRoutineAugIntf")),     UNUSED, false)
 DEF_VISA_OPTION(vISA_FastCompileRA,    ET_BOOL, (IGC_MANGLE("-fastCompileRA")),     UNUSED, false)
 DEF_VISA_OPTION(vISA_HybridRAWithSpill,    ET_BOOL, (IGC_MANGLE("-hybridRAWithSpill")),     UNUSED, false)
+
 //=== binary emission options ===
 DEF_VISA_OPTION(vISA_Compaction,          ET_BOOL,  "-nocompaction",    UNUSED, true)
 DEF_VISA_OPTION(vISA_BXMLEncoder,         ET_BOOL,  "-nobxmlencoder",   UNUSED, true)
@@ -231,6 +232,7 @@ DEF_VISA_OPTION(vISA_ReRAPostSchedule,    ET_BOOL,  "-rerapostschedule",  UNUSED
 DEF_VISA_OPTION(vISA_GTPinReRA,           ET_BOOL, "-GTPinReRA",          UNUSED, false)
 DEF_VISA_OPTION(vISA_GetFreeGRFInfo,      ET_BOOL,  "-getfreegrfinfo",    UNUSED, false)
 DEF_VISA_OPTION(vISA_GTPinScratchAreaSize,ET_INT32, "-GTPinScratchAreaSize", UNUSED, 0)
+DEF_VISA_OPTION(vISA_skipFenceCommit,     ET_BOOL,  "-skipFenceCommit", UNUSED, false)
 
 //=== HW Workarounds ===
 DEF_VISA_OPTION(vISA_clearScratchWritesBeforeEOT,   ET_BOOL,  NULLSTR, UNUSED, false)
@@ -253,7 +255,6 @@ DEF_VISA_OPTION(vISA_setStartBreakPoint,  ET_BOOL,  "-setstartbp",        UNUSED
 DEF_VISA_OPTION(vISA_InsertHashMovs,      ET_BOOL,  NULLSTR,              UNUSED, false)
 DEF_VISA_OPTION(vISA_InsertDummyMovForHWRSWA,      ET_BOOL,  "-insertRSDummyMov",              UNUSED, false)
 DEF_VISA_OPTION(vISA_registerHWRSWA,      ET_INT32,  "-dummyRegisterHWRSWA",              UNUSED, 0)
-//   insert a dummy instruction at the beginning
 DEF_VISA_OPTION(vISA_InsertDummyCompactInst, ET_BOOL, "-insertDummyCompactInst", UNUSED, false)
 DEF_VISA_OPTION(VISA_AsmFileNameUser,     ET_BOOL,  NULLSTR,        UNUSED, false)
 DEF_VISA_OPTION(vISA_HashVal,             ET_2xINT32, "-hashmovs", "USAGE: -hashmovs hi32 lo32\n", 0)