(NFCI) Avoid passing each basic block's scheduling stats in FINALIZER_INFO, second try.

vISA FINALIZER_INFO struct has each basic block's scheduling stats (weighted and
unweighted stall cycles), which is used by IGC both for stat reporting and also
in SIMD size selection heuristics. This requires a dynamic allocated array to
store the information. Avoid this by having vISA sum up the stats for the shader
instead. Also move the basic block count information in FINALIZER_INFO out of
the post-RA scheduler pass as it is not necessarily enabled always.

The first submission was backed out due to test regressions, but it seems the
test is unstable and has sporadic failures.

Author: Wei-Chen-Intel

IGC/Compiler/CISACodeGen/CISABuilder.cpp

@@ -6074,23 +6074,10 @@ namespace IGC
             SimdSize32++;
         }
 
-        uint sendStallCycle = 0;
-        uint staticCycle = 0;
-        uint loopNestedStallCycle = 0;
-        uint loopNestedCycle = 0;
-        for (uint i = 0; i < jitInfo->BBNum; i++)
-        {
-            sendStallCycle += jitInfo->BBInfo[i].sendStallCycle;
-            staticCycle += jitInfo->BBInfo[i].staticCycle;
-            // expects that a loop runs 16 iterations
-            auto nestingfactor = (jitInfo->BBInfo[i].loopNestLevel * 4);
-            loopNestedStallCycle += (jitInfo->BBInfo[i].sendStallCycle << nestingfactor);
-            loopNestedCycle += (jitInfo->BBInfo[i].staticCycle << nestingfactor);
-        }
-        m_program->m_sendStallCycle = sendStallCycle;
-        m_program->m_staticCycle = staticCycle;
-        m_program->m_loopNestedStallCycle = loopNestedStallCycle;
-        m_program->m_loopNestedCycle = loopNestedCycle;
+        m_program->m_sendStallCycle = jitInfo->stats.sendStallCycle;
+        m_program->m_staticCycle = jitInfo->stats.staticCycle;
+        m_program->m_loopNestedStallCycle = jitInfo->stats.loopNestedStallCycle;
+        m_program->m_loopNestedCycle = jitInfo->stats.loopNestedCycle;
 
         bool isStackCallProgram = m_program->HasStackCalls() || m_program->IsIntelSymbolTableVoidProgram();
         bool noRetry = jitInfo->avoidRetry;

visa/LocalScheduler/LocalScheduler_G4IR.cpp

@@ -17,23 +17,21 @@ SPDX-License-Identifier: MIT
 #include <functional>
 #include <queue>
 #include <sstream>
+#include <vector>
 
 using namespace vISA;
 
 /* Entry to the local scheduling. */
 void LocalScheduler::localScheduling() {
   // This is controlled by options for debugging
-  if (!fg.getKernel()->isLocalSheduleable()) {
+  if (!fg.getKernel()->isLocalSheduleable())
     return;
-  }
 
-  DEBUG_VERBOSE("[Scheduling]: Starting...");
+  VISA_DEBUG_VERBOSE(std::cout << "[Scheduling]: Starting...");
   BB_LIST_ITER ib(fg.begin()), bend(fg.end());
   vISA_ASSERT(ib != bend, ERROR_SCHEDULER);
 
-  VISA_BB_INFO *bbInfo =
-      (VISA_BB_INFO *)mem.alloc(fg.size() * sizeof(VISA_BB_INFO));
-  memset(bbInfo, 0, fg.size() * sizeof(VISA_BB_INFO));
+  std::vector<VISA_BB_INFO> bbInfo(fg.size());
   int i = 0;
 
   const Options *m_options = fg.builder->getOptions();
@@ -118,9 +116,26 @@ void LocalScheduler::localScheduling() {
 
     i++;
   }
+
+  // Sum up the cycles for each BB.
+  unsigned sendStallCycle = 0;
+  unsigned staticCycle = 0;
+  unsigned loopNestedStallCycle = 0;
+  unsigned loopNestedCycle = 0;
+  for (auto &bbStat : bbInfo) {
+    sendStallCycle += bbStat.sendStallCycle;
+    staticCycle += bbStat.staticCycle;
+    // Expect that a loop runs 16 iterations.
+    auto nestingfactor = (bbStat.loopNestLevel * 4);
+    loopNestedStallCycle += (bbStat.sendStallCycle << nestingfactor);
+    loopNestedCycle += (bbStat.staticCycle << nestingfactor);
+  }
+
   FINALIZER_INFO *jitInfo = fg.builder->getJitInfo();
-  jitInfo->BBInfo = bbInfo;
-  jitInfo->BBNum = i;
+  jitInfo->stats.sendStallCycle = sendStallCycle;
+  jitInfo->stats.staticCycle = staticCycle;
+  jitInfo->stats.loopNestedStallCycle = loopNestedStallCycle;
+  jitInfo->stats.loopNestedCycle = loopNestedCycle;
   jitInfo->stats.numCycles = totalCycles;
 }
 

visa/LocalScheduler/LocalScheduler_G4IR.h

@@ -330,14 +330,12 @@ class G4_BB_Schedule {
 
 class LocalScheduler {
   FlowGraph &fg;
-  Mem_Manager &mem;
 
   // send latencies are now defined in FFLatency in LIR.cpp
   void EmitNode(Node *);
 
 public:
-  LocalScheduler(FlowGraph &flowgraph, Mem_Manager &m)
-      : fg(flowgraph), mem(m) {}
+  LocalScheduler(FlowGraph &flowgraph) : fg(flowgraph) {}
   void localScheduling();
 };
 

visa/Optimizer.h

@@ -157,7 +157,7 @@ class Optimizer {
     }
   }
   void localSchedule() {
-    LocalScheduler lSched(kernel.fg, mem);
+    LocalScheduler lSched(kernel.fg);
     lSched.localScheduling();
   }
 

visa/VISAKernelImpl.cpp

@@ -661,10 +661,12 @@ void VISAKernelImpl::dumpPerfStatsInJson(const std::string &filename) {
 }
 
 void VISAKernelImpl::recordFinalizerInfo() {
-  if (m_builder->getJitInfo()) {
-    m_builder->getJitInfo()->stats.numAsmCountUnweighted = m_kernel->getAsmCount();
-    m_builder->getJitInfo()->stats.numGRFTotal = m_kernel->getNumRegTotal();
-    m_builder->getJitInfo()->stats.numThreads = m_kernel->getNumThreads();
+  auto jitInfo = m_builder->getJitInfo();
+  if (jitInfo) {
+    jitInfo->stats.numAsmCountUnweighted = m_kernel->getAsmCount();
+    jitInfo->stats.numGRFTotal = m_kernel->getNumRegTotal();
+    jitInfo->stats.numThreads = m_kernel->getNumThreads();
+    jitInfo->BBNum = static_cast<uint32_t>(m_kernel->fg.size());
   }
 }
 

visa/include/JitterDataStruct.h

@@ -61,6 +61,16 @@ struct PERF_STATS {
 
   uint32_t maxGRFPressure = 0;
 
+  // These fields are currently used by IGC.
+  // The first two are unweighted (i.e., just a sum of each basic block's
+  // estimated cycles), while the last two are weighted by loop (16 iterations
+  // per loop).
+  // Note that these stats are valid only if post-RA scheduling is enabled.
+  uint32_t sendStallCycle = 0;
+  uint32_t staticCycle = 0;
+  uint32_t loopNestedStallCycle = 0;
+  uint32_t loopNestedCycle = 0;
+
 public:
   llvm::json::Value toJSON();
 };
@@ -70,10 +80,10 @@ struct PERF_STATS {
 // queried (vISA_DumpPerfStatsVerbose)
 // TODO: This set will be disable completely in the Release build.
 struct PERF_STATS_VERBOSE {
- // The number of bank conflict.
+  // The number of bank conflict.
   unsigned BCNum = 0;
 
- // counting the number of read-modify-write
+  // counting the number of read-modify-write
   unsigned numRMWs = 0;
 
   // For the static profiling of acc regsiter substituion ratio
@@ -129,8 +139,9 @@ struct FINALIZER_INFO {
   // This information is used by legacy CMRT as well as OpenCL/L0 runtime.
   uint32_t numBarriers = 0;
 
-  // Unweighted BB cycles counts. Used by IGC for SIMD width selection.
+  // Number of basic blocks in the kernel, used by IGC for stat reporting.
   uint32_t BBNum = 0;
+  // TODO: this is no longer used, can we remove them without breaking stuff?
   VISA_BB_INFO *BBInfo = nullptr;
 
   // Whether kernel recompilation should be avoided. vISA hint for IGC.
@@ -160,6 +171,5 @@ struct FINALIZER_INFO {
   PERF_STATS_VERBOSE statsVerbose;
 };
 
-
 } // namespace vISA
 #endif // JITTERDATASTRUCT_