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Konstantin Vladimirovigcbot
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Fix memory overwriting in TPM
1 parent 8ae40d2 commit 410fcee

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4 files changed

+36
-22
lines changed

4 files changed

+36
-22
lines changed

IGC/VectorCompiler/include/vc/GenXOpts/Utils/InternalMetadata.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,13 @@ inline constexpr const char VCEmulationRoutine[] = "VC.Emulation.Routine";
2424
}
2525

2626
namespace InstMD {
27+
// SVMBlockType metadata serves interesting purpose:
28+
// Finalizer now don't support properly SVM gathers/scatters less then dword
29+
// So we are extending everything to 32 but preserving real type in metadata
30+
// To use it later in CISA builder when we are creating gather/scatter
2731
inline constexpr const char SVMBlockType[] = "SVMBlockType";
32+
33+
// These two are used in prologue/epilogue insertion
2834
inline constexpr const char FuncArgSize[] = "FuncArgSize";
2935
inline constexpr const char FuncRetSize[] = "FuncRetSize";
3036
}

IGC/VectorCompiler/lib/GenXCodeGen/GenXCisaBuilder.cpp

Lines changed: 17 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -3710,21 +3710,31 @@ void GenXKernelBuilder::buildIntrinsic(CallInst *CI, unsigned IntrinID,
37103710
return Byte;
37113711
};
37123712

3713-
auto GetSvmGatherBlockSize = [&](II::ArgInfo AI) {
3714-
LLVM_DEBUG(dbgs() << "GetSvmGatherBlockSize\n");
3713+
auto GetSvmBlockSizeNum = [&](II::ArgInfo Sz, II::ArgInfo Num) {
3714+
LLVM_DEBUG(dbgs() << "SVM gather/scatter element size and num blocks\n");
37153715
// svm gather/scatter "block size" field, set to reflect the element
37163716
// type of the data
37173717
Value *V = CI;
3718-
if (!AI.isRet())
3719-
V = CI->getArgOperand(AI.getArgIdx());
3718+
if (!Sz.isRet())
3719+
V = CI->getArgOperand(Sz.getArgIdx());
37203720
auto *EltType = V->getType()->getScalarType();
37213721
if (auto *MDType = CI->getMetadata(InstMD::SVMBlockType))
37223722
EltType = cast<ValueAsMetadata>(MDType->getOperand(0).get())->getType();
3723+
ConstantInt *LogOp = cast<ConstantInt>(CI->getArgOperand(Num.getArgIdx()));
3724+
unsigned LogNum = LogOp->getZExtValue();
37233725
unsigned ElBytes = getResultedTypeSize(EltType, DL);
37243726
switch (ElBytes) {
3725-
// For N = 2 byte data type, use block size 1 and block count 2.
3726-
// Otherwise, use block size N and block count 1.
3727+
// For N = 2 byte data type, use block size 1 and block count x2
3728+
// Otherwise, use block size N and original block count.
37273729
case 2:
3730+
ElBytes = 0;
3731+
IGC_ASSERT(LogNum < 4);
3732+
// This is correct but I can not merge this in while ISPC not fixed
3733+
// LogNum += 1;
3734+
3735+
// this is incorrect temporary solution
3736+
LogNum = 1;
3737+
break;
37283738
case 1:
37293739
ElBytes = 0;
37303740
break;
@@ -3739,7 +3749,7 @@ void GenXKernelBuilder::buildIntrinsic(CallInst *CI, unsigned IntrinID,
37393749
DS_Error};
37403750
getContext().diagnose(Err);
37413751
}
3742-
return ElBytes;
3752+
return std::make_pair(ElBytes, LogNum);
37433753
};
37443754

37453755
auto CreateOpndPredefinedSrc = [&](PreDefined_Vars RegId, unsigned ROffset,

IGC/VectorCompiler/lib/GenXCodeGen/GenXThreadPrivateMemory.cpp

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -620,11 +620,8 @@ bool GenXThreadPrivateMemory::replaceLoad(LoadInst *LdI) {
620620

621621
Value *EltsOffset = FormEltsOffsetVector(NumEltsToLoad, ValueEltSz, LdI);
622622

623-
unsigned NumBlocks = m_DL->getTypeSizeInBits(LdEltTy) / genx::ByteBits;
624-
// This logic is aligned with the on in CisaBuilder and GenXLowering
625-
// The reason behind check for == 2 is that svm intrinsics don't support
626-
// BlockSize of 2, so for ops with i16s we have to use BlockSize == 1 and NumBlocks == 2
627-
Value *logNumBlocks = ConstantInt::get(I32Ty, genx::log2(NumBlocks == 2 ? NumBlocks : 1));
623+
// always one element for one channel
624+
Value *logNumBlocks = ConstantInt::get(I32Ty, 0);
628625
Value *Scale = ConstantInt::get(Type::getInt16Ty(*m_ctx), 0);
629626
Value *Surface = ConstantInt::get(I32Ty,
630627
visa::getReservedSurfaceIndex(m_stack));
@@ -715,9 +712,9 @@ bool GenXThreadPrivateMemory::replaceStore(StoreInst *StI) {
715712
{Pred->getType(),
716713
(m_useGlobalMem ? Offset : EltsOffset)->getType(),
717714
ValueOp->getType()});
718-
unsigned NumBlocks = m_DL->getTypeSizeInBits(ValueOpTy->getScalarType()) / genx::ByteBits;
719-
// see the comment in replaceLoad above
720-
Value *logNumBlocks = ConstantInt::get(I32Ty, genx::log2(NumBlocks == 2 ? NumBlocks : 1));
715+
716+
// always one element for one channel
717+
Value *logNumBlocks = ConstantInt::get(I32Ty, 0);
721718
Value *Scale = ConstantInt::get(Type::getInt16Ty(*m_ctx), 0);
722719
Value *Surface = ConstantInt::get(I32Ty,
723720
visa::getReservedSurfaceIndex(m_stack));

IGC/VectorCompiler/lib/GenXCodeGen/Utils/cisa_gen_intrinsics.json

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2308,7 +2308,6 @@
23082308
"sub_opc": [ "LITERAL", "SVM_GATHER" ],
23092309
"exec_size": [ "EXECSIZE_FROM_ARG", 1 ],
23102310
"pred": [ "PREDICATION", 1 ],
2311-
"block_size_inferred_from_dst": [ "SVMGATHERBLOCKSIZE", 0 ],
23122311
"log2_num_blocks": [ "BYTE", 2 ],
23132312
"address": [ "URAW", 3 ],
23142313
"twoaddr": [ "TWOADDR", 4 ],
@@ -2333,7 +2332,6 @@
23332332
"sub_opc": [ "LITERAL", "SVM_SCATTER" ],
23342333
"exec_size": [ "EXECSIZE_FROM_ARG", 1 ],
23352334
"pred": [ "PREDICATION", 1 ],
2336-
"block_size_inferred_from_dst": [ "SVMGATHERBLOCKSIZE", 4 ],
23372335
"log2_num_blocks": [ "BYTE", 2 ],
23382336
"address": [ "URAW", 3 ],
23392337
"src": [ "RAW", 4 ]
@@ -3809,13 +3807,15 @@
38093807
]
38103808
],
38113809
"ISA_SVM_SVM_GATHER": [
3810+
"unsigned BlockType, BlockNum",
3811+
"std::tie(BlockType, BlockNum) = GetSvmBlockSizeNum(II::ArgInfo(II::GENERAL | 0), II::ArgInfo(II::GENERAL | 2))",
38123812
[ "CISA_CALL",
38133813
[ "Kernel->AppendVISASvmGatherInst",
38143814
"pred",
38153815
"exec_mask",
38163816
"exec_size",
3817-
"(VISA_SVM_Block_Type)block_size_inferred_from_dst",
3818-
"(VISA_SVM_Block_Num)log2_num_blocks",
3817+
"(VISA_SVM_Block_Type)BlockType",
3818+
"(VISA_SVM_Block_Num)BlockNum",
38193819
"address",
38203820
"dst"
38213821
]
@@ -3835,13 +3835,15 @@
38353835
]
38363836
],
38373837
"ISA_SVM_SVM_SCATTER": [
3838+
"unsigned BlockType, BlockNum",
3839+
"std::tie(BlockType, BlockNum) = GetSvmBlockSizeNum(II::ArgInfo(II::GENERAL | 4), II::ArgInfo(II::GENERAL | 2))",
38383840
[ "CISA_CALL",
38393841
[ "Kernel->AppendVISASvmScatterInst",
38403842
"pred",
38413843
"exec_mask",
38423844
"exec_size",
3843-
"(VISA_SVM_Block_Type)block_size_inferred_from_dst",
3844-
"(VISA_SVM_Block_Num)log2_num_blocks",
3845+
"(VISA_SVM_Block_Type)BlockType",
3846+
"(VISA_SVM_Block_Num)BlockNum",
38453847
"address",
38463848
"src"
38473849
]
@@ -3901,7 +3903,6 @@
39013903
"INT": "GetUnsignedValue(II::ArgInfo({args}))",
39023904
"LOG2OWORDS": "GetOwords(II::ArgInfo({args}))",
39033905
"LOG2OWORDS_PLUS_8": "GetOwords(II::ArgInfo({args})) + 8",
3904-
"SVMGATHERBLOCKSIZE": "GetSvmGatherBlockSize(II::ArgInfo({args}))",
39053906
"TWOADDR": "ProcessTwoAddr(II::ArgInfo({args}))",
39063907
"CONSTVI1ASI32": "ConstVi1Asi32(II::ArgInfo({args}))",
39073908
"ARGCOUNT": "GetArgCount(II::ArgInfo({args}))",

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