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pratikasharsys_zuul
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Fix number of elements to use in G4_Declare creation in remat.
Change-Id: Id8b25add97460a950a67df349ad16f5f783c2477
1 parent 8ee5460 commit 26a6505

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2 files changed

+6
-6
lines changed

2 files changed

+6
-6
lines changed

visa/RegAlloc.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -3813,17 +3813,17 @@ int regAlloc(IR_Builder& builder, PhyRegPool& regPool, G4_Kernel& kernel)
38133813
jitInfo->numBytesScratchGtpin = kernel.getGTPinData()->getNumBytesScratchUse();
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}
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3816-
if (auto sp = kernel.getVarSplitPass())
3817-
{
3818-
sp->replaceIntrinsics();
3819-
}
3820-
38213816
recordRAStats(builder, kernel, status);
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if (status != VISA_SUCCESS)
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{
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return status;
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}
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3822+
if (auto sp = kernel.getVarSplitPass())
3823+
{
3824+
sp->replaceIntrinsics();
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}
3826+
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if (builder.getOption(vISA_VerifyRA))
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{
38293829
LivenessAnalysis liveAnalysis(gra,

visa/Rematerialization.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -900,7 +900,7 @@ namespace vISA
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MUST_BE_TRUE(ops != operations.end(), "Didnt find record in map");
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MUST_BE_TRUE((*ops).second.numUses == 1, "Expecting src0 to be used only in sampler");
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903-
auto newSrc0Dcl = kernel.fg.builder->createTempVar(src0TopDcl->getNumElems(),
903+
auto newSrc0Dcl = kernel.fg.builder->createTempVar(src0TopDcl->getTotalElems(),
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src0TopDcl->getElemType(), gra.getSubRegAlign(src0TopDcl));
905905

906906
// Clone all defining instructions for sampler's msg header

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