Proper SIMD width for enabling forceBCR

Our information on maximal register pressure is based on minimal SIMD width
so it needs to be adjusted to the one that we really compile to.

Author: ekochetk

IGC/Compiler/CISACodeGen/CISABuilder.cpp

@@ -8,6 +8,7 @@ SPDX-License-Identifier: MIT
 
 #include "Compiler/CISACodeGen/CISABuilder.hpp"
 #include "Compiler/CISACodeGen/ShaderCodeGen.hpp"
+#include "Compiler/CISACodeGen/IGCLivenessAnalysis.h"
 #include "Compiler/CISACodeGen/OpenCLKernelCodeGen.hpp"
 #include "Compiler/Optimizer/OpenCLPasses/NamedBarriers/NamedBarriersResolution.hpp"
 #include "common/allocator.h"
@@ -3545,8 +3546,8 @@ void CEncoder::SetAbortOnSpillThreshold(bool canAbortOnSpill, bool AllowSpill) {
   }
 }
 
-void CEncoder::InitVISABuilderOptions(TARGET_PLATFORM VISAPlatform, bool canAbortOnSpill, bool hasStackCall,
-                                      bool enableVISA_IR) {
+void CEncoder::InitVISABuilderOptions(TARGET_PLATFORM VISAPlatform, SIMDMode simdMode, bool canAbortOnSpill,
+                                      bool hasStackCall, bool enableVISA_IR) {
   CodeGenContext *context = m_program->GetContext();
   bool KernelDebugEnable = false;
   bool ForceNonCoherentStatelessBti = false;
@@ -4239,13 +4240,16 @@ void CEncoder::InitVISABuilderOptions(TARGET_PLATFORM VISAPlatform, bool canAbor
 
   auto funcInfoMD = context->getMetaDataUtils()->getFunctionsInfoItem(m_program->entry);
   uint32_t MaxRegPressure = funcInfoMD->getMaxRegPressure()->getMaxPressure();
+  // need to adjust since MaxRegPressure assumes minimal SIMD
+  auto guessedSimd = IGCLivenessAnalysisBase::bestGuessSIMDSize(context, context->getMetaDataUtils(), m_program->entry);
+  MaxRegPressure = MaxRegPressure * numLanes(simdMode) / numLanes(guessedSimd);
   uint32_t RegPressureThreshold = (uint32_t)(context->getNumGRFPerThread(true) * 0.6);
-
+  bool maxPressureHeur = MaxRegPressure > 0 && MaxRegPressure < RegPressureThreshold &&
+                         m_program->GetParent()->getLLVMFunction()->size() == 1;
   if (context->type == ShaderType::OPENCL_SHADER &&
-      (m_program->m_Platform->limitedBCR() || (MaxRegPressure > 0 && MaxRegPressure < RegPressureThreshold))) {
+      (m_program->m_Platform->limitedBCR() || (maxPressureHeur))) {
     SaveOption(vISA_enableBCR, true);
-    if (m_program->GetParent()->getLLVMFunction()->size() == 1 &&
-        m_program->m_Platform->getMinDispatchMode() != SIMDMode::SIMD8)
+    if (m_program->m_Platform->getMinDispatchMode() != SIMDMode::SIMD8)
       SaveOption(vISA_forceBCR, true);
   }
   if (context->type == ShaderType::OPENCL_SHADER && m_program->m_Platform->supportDpasInstruction()) {
@@ -4722,7 +4726,7 @@ void CEncoder::InitLabelMap(const llvm::Function *F) {
   }
 }
 
-void CEncoder::InitEncoder(bool canAbortOnSpill, bool hasStackCall, bool hasInlineAsmCall,
+void CEncoder::InitEncoder(SIMDMode simdMode, bool canAbortOnSpill, bool hasStackCall, bool hasInlineAsmCall,
                            bool hasAdditionalVisaAsmToLink, int numThreadsPerEU, uint lowerBoundGRF, uint upperBoundGRF,
                            VISAKernel *prevKernel) {
   m_aliasesMap.clear();
@@ -4770,7 +4774,7 @@ void CEncoder::InitEncoder(bool canAbortOnSpill, bool hasStackCall, bool hasInli
   if (IsCodePatchCandidate()) {
     SetHasPrevKernel(prevKernel != nullptr);
   }
-  InitVISABuilderOptions(VISAPlatform, canAbortOnSpill, hasStackCall, builderOpt == VISA_BUILDER_BOTH);
+  InitVISABuilderOptions(VISAPlatform, simdMode, canAbortOnSpill, hasStackCall, builderOpt == VISA_BUILDER_BOTH);
 
   if (numThreadsPerEU > 0) {
     // Number of threads per EU is set per kernel (by function MD)

IGC/Compiler/CISACodeGen/CISABuilder.hpp

@@ -118,10 +118,11 @@ struct SEncoderState {
 
 class CEncoder {
 public:
-  void InitEncoder(bool canAbortOnSpill, bool hasStackCall, bool hasInlineAsmCall, bool hasAdditionalVisaAsmToLink,
-                   int numThreadsPerEU, uint lowerBoundGRF, uint upperBoundGRF, VISAKernel *prevKernel);
+  void InitEncoder(SIMDMode simdMode, bool canAbortOnSpill, bool hasStackCall, bool hasInlineAsmCall,
+                   bool hasAdditionalVisaAsmToLink, int numThreadsPerEU, uint lowerBoundGRF, uint upperBoundGRF,
+                   VISAKernel *prevKernel);
   void InitBuildParams(llvm::SmallVector<std::unique_ptr<const char, std::function<void(const char *)>>, 10> &params);
-  void InitVISABuilderOptions(TARGET_PLATFORM VISAPlatform, bool canAbortOnSpill, bool hasStackCall,
+  void InitVISABuilderOptions(TARGET_PLATFORM VISAPlatform, SIMDMode simdMode, bool canAbortOnSpill, bool hasStackCall,
                               bool enableVISA_IR);
   SEncoderState CopyEncoderState();
   void SetEncoderState(SEncoderState &newState);

IGC/Compiler/CISACodeGen/EmitVISAPass.cpp

@@ -773,7 +773,7 @@ bool EmitPass::runOnFunction(llvm::Function &F) {
     }
     // call builder after pre-analysis pass where scratchspace offset to VISA is
     // calculated
-    m_encoder->InitEncoder(m_canAbortOnSpill, m_currShader->HasStackCalls(), hasInlineAsmCall,
+    m_encoder->InitEncoder(m_SimdMode, m_canAbortOnSpill, m_currShader->HasStackCalls(), hasInlineAsmCall,
                            hasAdditionalVisaAsmToLink, numThreadsPerEU, lowerBoundGRF, upperBoundGRF, prevKernel);
 
     if (!m_encoder->IsCodePatchCandidate())

IGC/Compiler/CISACodeGen/IGCLivenessAnalysis.cpp

@@ -45,7 +45,8 @@ unsigned int IGCLivenessAnalysisBase::registerSizeInBytes() {
   return 32;
 }
 
-SIMDMode IGCLivenessAnalysisBase::bestGuessSIMDSize(Function *F) {
+SIMDMode IGCLivenessAnalysisBase::bestGuessSIMDSize(IGC::CodeGenContext *CGCtx, IGCMD::MetaDataUtils *MDUtils,
+                                                    Function *F, GenXFunctionGroupAnalysis *FGA) {
   switch (IGC_GET_FLAG_VALUE(ForceOCLSIMDWidth)) {
   case 0:
     break;
@@ -69,19 +70,23 @@ SIMDMode IGCLivenessAnalysisBase::bestGuessSIMDSize(Function *F) {
   if (CGCtx->platform.isProductChildOf(IGFX_PVC)) {
     bool abortOnSpills =
         IGC_GET_FLAG_VALUE(AllowSIMD16DropForXE2Plus) && (CGCtx->platform.isCoreXE2() || CGCtx->platform.isCoreXE3());
-    auto FG = FGA ? FGA->getGroup(F) : nullptr;
-    bool hasStackCall = (FG && FG->hasStackCall()) || (F && F->hasFnAttribute("visaStackCall"));
-    bool isIndirectGroup = FG && FGA->isIndirectCallGroup(FG);
-    bool hasSubroutine = FG && !FG->isSingle() && !hasStackCall && !isIndirectGroup;
-    if (abortOnSpills || hasSubroutine) {
+    if (abortOnSpills)
       return SIMDMode::SIMD16;
+    if (FGA) {
+      auto FG = FGA ? FGA->getGroup(F) : nullptr;
+      bool hasStackCall = (FG && FG->hasStackCall()) || (F && F->hasFnAttribute("visaStackCall"));
+      bool isIndirectGroup = FG && FGA->isIndirectCallGroup(FG);
+      bool hasSubroutine = FG && !FG->isSingle() && !hasStackCall && !isIndirectGroup;
+      if (hasSubroutine)
+        return SIMDMode::SIMD16;
     }
     return SIMDMode::SIMD32;
   }
-
   return SIMDMode::SIMD8;
 }
 
+SIMDMode IGCLivenessAnalysisBase::bestGuessSIMDSize(Function *F) { return bestGuessSIMDSize(CGCtx, MDUtils, F, FGA); }
+
 ValueSet IGCLivenessAnalysisBase::getDefs(llvm::BasicBlock &BB) {
 
   ValueSet &BBIn = In[&BB];

IGC/Compiler/CISACodeGen/IGCLivenessAnalysis.h

@@ -63,9 +63,9 @@ class IGCLivenessAnalysisBase {
   unsigned int estimateSizeInBytes(ValueSet &Set, llvm::Function &F, unsigned int SIMD, WIAnalysisRunner *WI = nullptr);
   void collectPressureForBB(llvm::BasicBlock &BB, InsideBlockPressureMap &BBListing, unsigned int SIMD,
                             WIAnalysisRunner *WI = nullptr);
-
   SIMDMode bestGuessSIMDSize(Function *F = nullptr);
-
+  static SIMDMode bestGuessSIMDSize(IGC::CodeGenContext *CGCtx, IGCMD::MetaDataUtils *MDUtils, Function *F = nullptr,
+                                    GenXFunctionGroupAnalysis *FGA = nullptr);
   unsigned int bytesToRegisters(unsigned int Bytes) {
     unsigned int RegisterSizeInBytes = registerSizeInBytes();
     unsigned int AmountOfRegistersRoundUp = (Bytes + RegisterSizeInBytes - 1) / RegisterSizeInBytes;