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WaveShuffleIndex Sinking Optimization
Hoists and combines some identical BinaryOperator instructions that come after WaveShuffleIndex instructions with a constant lane/channel and sink WaveShuffleIndex instrucitons to the point of divergence Use distributive property of insturctions to allow some BinaryOperators to be hoisted above other unhoistable BinaryOperators
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‎IGC/Compiler/CISACodeGen/ShaderCodeGen.cpp‎

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@@ -101,6 +101,7 @@ SPDX-License-Identifier: MIT
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#include "Compiler/Optimizer/SynchronizationObjectCoalescing.hpp"
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#include "Compiler/Optimizer/BarrierControlFlowOptimization.hpp"
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#include "Compiler/Optimizer/RuntimeValueVectorExtractPass.h"
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#include "Compiler/Optimizer/WaveShuffleIndexSinking.hpp"
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#include "Compiler/MetaDataApi/PurgeMetaDataUtils.hpp"
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#include "Compiler/HandleLoadStoreInstructions.hpp"
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#include "Compiler/CustomSafeOptPass.hpp"
@@ -1424,6 +1425,10 @@ void OptimizeIR(CodeGenContext* const pContext)
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}
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mpm.add(createIGCInstructionCombiningPass());
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if( IGC_IS_FLAG_ENABLED( EnableWaveShuffleIndexSinking ) )
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{
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mpm.add( createWaveShuffleIndexSinking() );
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}
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mpm.add(new FCmpPaternMatch());
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mpm.add(llvm::createDeadCodeEliminationPass()); // this should be done both before/after constant propagation
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‎IGC/Compiler/InitializePasses.h‎

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@@ -273,3 +273,4 @@ void initializeCollectLoopCountPass(llvm::PassRegistry&);
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void initializeRemoveLoopDependencyPass(llvm::PassRegistry&);
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void initializeResourceLoopUnrollPass(llvm::PassRegistry&);
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void initializeInjectPrintfPass(llvm::PassRegistry&);
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void initializeWaveShuffleIndexSinkingPass(llvm::PassRegistry&);

‎IGC/Compiler/Optimizer/CMakeLists.txt‎

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@@ -33,6 +33,7 @@ set(IGC_BUILD__SRC__Optimizer
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"${CMAKE_CURRENT_SOURCE_DIR}/ValueTracker.cpp"
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"${CMAKE_CURRENT_SOURCE_DIR}/RuntimeValueVectorExtractPass.cpp"
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"${CMAKE_CURRENT_SOURCE_DIR}/BarrierControlFlowOptimization.cpp"
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"${CMAKE_CURRENT_SOURCE_DIR}/WaveShuffleIndexSinking.cpp"
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)
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set(IGC_BUILD__SRC__Compiler_Optimizer
@@ -59,6 +60,7 @@ set(IGC_BUILD__HDR__Optimizer
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"${CMAKE_CURRENT_SOURCE_DIR}/ValueTracker.h"
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"${CMAKE_CURRENT_SOURCE_DIR}/RuntimeValueVectorExtractPass.h"
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"${CMAKE_CURRENT_SOURCE_DIR}/BarrierControlFlowOptimization.hpp"
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"${CMAKE_CURRENT_SOURCE_DIR}/WaveShuffleIndexSinking.cpp"
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)
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set(IGC_BUILD__HDR__Optimizer

‎IGC/Compiler/Optimizer/WaveShuffleIndexSinking.cpp‎

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‎IGC/Compiler/Optimizer/WaveShuffleIndexSinking.hpp‎

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/*========================== begin_copyright_notice ============================
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Copyright (C) 2024 Intel Corporation
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SPDX-License-Identifier: MIT
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============================= end_copyright_notice ===========================*/
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#pragma once
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#include "common/LLVMWarningsPush.hpp"
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#include <llvm/Pass.h>
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#include "common/LLVMWarningsPop.hpp"
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namespace IGC
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{
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llvm::FunctionPass* createWaveShuffleIndexSinking();
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} // namespace IGC

‎IGC/Compiler/tests/WaveShuffleIndexSinking/basic.ll‎

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;=========================== begin_copyright_notice ============================
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;
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; Copyright (C) 2024 Intel Corporation
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;
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; SPDX-License-Identifier: MIT
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;
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;============================ end_copyright_notice =============================
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; RUN: igc_opt -igc-wave-shuffle-index-sinking -S < %s | FileCheck %s
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; ------------------------------------------------
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; WaveShuffleIndexSinking
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;
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; Verifies that four WaveShuffleIndex instructions with the same source and a constant channel get subsequent instructions checked and hoisted
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; Each WaveShuffleIndex instruction is in turn fed into an add, and then a shl
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; The second operand of the add is not a constant, so the add is considered an anchor instruction
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; The second operand of the shl is a constant, so the shl is considered a hoistable instruction
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; Due to distributive properties, the shl is allowed to be hoisted above the add, and afterwards, above all the WaveShuffleIndex instructions
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; Since there are 4 WaveShuffleIndex instructions in the ShuffleGroup, we can trade a shl on the source of the WaveShuffleIndex and a shl on the second operand of the add for removing all 4 shl instructions operating on the result of each add
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; This changes the number of instructions from 4 * WSI + 4 * add + 4 * shl to shl(for %a) + shl(for %b) + 4 * WS + 4 * add, reducing the total number of instructions by 2, while preserving functionality
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; ------------------------------------------------
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define void @test_wave_shuffle_index_sinking(i32* %dst0, i32* %dst1, i32* %dst2, i32* %dst3, i32 %a, i32 %b) {
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; CHECK: [[HOISTED:%.*]] = shl i32 %a, 2
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; CHECK: [[WS0:%.*]] = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 [[HOISTED]], i32 0, i32 0)
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%ws0 = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 %a, i32 0, i32 0)
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; CHECK: [[ANCHOR_HOISTED:%.*]] = shl i32 %b, 2
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; CHECK-NEXT: [[ANCHOR0:%.*]] = add i32 [[WS0]], [[ANCHOR_HOISTED]]
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%add0 = add i32 %ws0, %b
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%shl0 = shl i32 %add0, 2
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; CHECK: store i32 [[ANCHOR0]], i32* %dst0
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store i32 %shl0, i32* %dst0
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; CHECK: [[WS1:%.*]] = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 [[HOISTED]], i32 1, i32 0)
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%ws1 = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 %a, i32 1, i32 0)
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; CHECK: [[ANCHOR1:%.*]] = add i32 [[WS1]], [[ANCHOR_HOISTED]]
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%add1 = add i32 %ws1, %b
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%shl1 = shl i32 %add1, 2
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; CHECK: store i32 [[ANCHOR1]], i32* %dst1
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store i32 %shl1, i32* %dst1
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; CHECK: [[WS2:%.*]] = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 [[HOISTED]], i32 2, i32 0)
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%ws2 = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 %a, i32 2, i32 0)
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; CHECK: [[ANCHOR2:%.*]] = add i32 [[WS2]], [[ANCHOR_HOISTED]]
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%add2 = add i32 %ws2, %b
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%shl2 = shl i32 %add2, 2
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; CHECK: store i32 [[ANCHOR2]], i32* %dst2
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store i32 %shl2, i32* %dst2
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; CHECK: [[WS3:%.*]] = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 [[HOISTED]], i32 3, i32 0)
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%ws3 = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 %a, i32 3, i32 0)
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; CHECK: [[ANCHOR3:%.*]] = add i32 [[WS3]], [[ANCHOR_HOISTED]]
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%add3 = add i32 %ws3, %b
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%shl3 = shl i32 %add3, 2
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; CHECK: store i32 [[ANCHOR3]], i32* %dst3
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store i32 %shl3, i32* %dst3
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ret void
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}
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; Function Attrs: convergent nounwind readnone
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declare i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32, i32, i32) #0
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attributes #0 = { convergent nounwind readnone }

‎IGC/Compiler/tests/WaveShuffleIndexSinking/split-sink-merge.ll‎

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;=========================== begin_copyright_notice ============================
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;
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; Copyright (C) 2024 Intel Corporation
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;
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; SPDX-License-Identifier: MIT
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;
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;============================ end_copyright_notice =============================
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; RUN: igc_opt -igc-wave-shuffle-index-sinking -S < %s | FileCheck %s
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; ------------------------------------------------
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; WaveShuffleIndexSinking
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;
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; This test does not primarily demonstrate the benefits/profitability of the optimization
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; This test focuses on the auxiliary functionality of splitting and merging various WaveShuffleIndex instructions
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; Only the 4 combinations of N/N, N/Y, Y/N, and Y/Y for Split/Merge need to be considered, Sink is for informational purposes only
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;
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; Test Scenarios
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; %ws0: Split: N, Sink: Y, Merge: N
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; %ws1: Split: Y, Sink: Y/Y, Merge: N (profitable to sink both paths)
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; %ws2: Split: Y, Sink: Y/N, Merge: N (profitable to sink one path)
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; %ws3: Split: Y, Sink: N/N, Merge: Y (nothing to group and sink with)
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; %ws4: Split: N, Sink: N, Merge: Y
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; %ws5: Split: N, Sink: N, Merge: Y
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; ------------------------------------------------
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define void @test_split_sink_merge(i32 %a, i32 %b, i32 %c, i32 %d) {
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; CHECK: [[USE1_WS0_WS1C1_HOISTED:%.*]] = shl i32 %a, 2
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; CHECK: [[WS0:%.*]] = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 [[USE1_WS0_WS1C1_HOISTED]], i32 0, i32 0)
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%ws0 = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 %a, i32 0, i32 0)
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%use1_ws0 = shl i32 %ws0, 2
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; CHECK: add i32 [[WS0]], %c
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%anchor1_ws0 = add i32 %use1_ws0, %c
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; CHECK: [[WS1C1:%.*]] = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 [[USE1_WS0_WS1C1_HOISTED]], i32 1, i32 0)
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%ws1 = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 %a, i32 1, i32 0)
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%use1_ws1 = shl i32 %ws1, 2
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; CHECK: add i32 [[WS1C1]], %c
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%anchor1_ws1 = add i32 %use1_ws1, %c
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; CHECK: [[USE2_WS1C2_WS2C1_HOISTED:%.*]] = shl i32 %a, 3
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; CHECK: [[WS1C2:%.*]] = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 [[USE2_WS1C2_WS2C1_HOISTED]], i32 1, i32 0)
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%use2_ws1 = shl i32 %ws1, 3
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; CHECK: add i32 [[WS1C2]], %d
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%anchor2_ws1 = add i32 %use2_ws1, %d
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; CHECK: [[WS2C1:%.*]] = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 [[USE2_WS1C2_WS2C1_HOISTED]], i32 2, i32 0)
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%ws2 = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 %a, i32 2, i32 0)
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%use1_ws2 = shl i32 %ws2, 3
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; CHECK: add i32 [[WS2C1]], %d
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%anchor1_ws2 = add i32 %use1_ws2, %d
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; CHECK: [[WS2C2:%.*]] = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 %a, i32 2, i32 0)
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; CHECK: [[USE2_WS2C2_NOT_HOISTED:%.*]] = shl i32 [[WS2C2]], 4
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%use2_ws2 = shl i32 %ws2, 4
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; CHECK: add i32 [[USE2_WS2C2_NOT_HOISTED]], %d
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%anchor2_ws2 = add i32 %use2_ws2, %d
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; CHECK: [[WS3:%.*]] = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 %b, i32 0, i32 0)
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%ws3 = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 %b, i32 0, i32 0)
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; CHECK-NEXT: add i32 [[WS3]], %c
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%use1_ws3 = add i32 %ws3, %c
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; CHECK-NEXT: add i32 [[WS3]], %d
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%use2_ws3 = add i32 %ws3, %d
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; CHECK: [[WS4:%.*]] = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 %b, i32 1, i32 0)
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%ws4 = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 %b, i32 1, i32 0)
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; CHECK-NEXT: {{%.*}} = add i32 [[WS4]], %c
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%use1_ws4 = add i32 %ws4, %c
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; CHECK-NOT: call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 %b, i32 1, i32 0)
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%ws5 = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 %b, i32 1, i32 0)
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; CHECK-NEXT: {{%.*}} = add i32 [[WS4]], %d
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%use1_ws5 = add i32 %ws5, %d
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ret void
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}
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; Function Attrs: convergent nounwind readnone
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declare i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32, i32, i32) #0
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attributes #0 = { convergent nounwind readnone }

‎IGC/Compiler/tests/WaveShuffleIndexSinking/two-iterations-delay.ll‎

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;=========================== begin_copyright_notice ============================
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;
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; Copyright (C) 2024 Intel Corporation
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;
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; SPDX-License-Identifier: MIT
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;
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;============================ end_copyright_notice =============================
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; RUN: igc_opt -igc-wave-shuffle-index-sinking -S < %s | FileCheck %s
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; ------------------------------------------------
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; WaveShuffleIndexSinking
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;
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; A new WaveShuffleInstruction may match with more hoistable instructions when compared to some individual WaveShuffleIndex insts in an existing ShuffleGroup
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; However, the group's maximal list of hoistable instructions is already established, and can only be reduced as more WaveShuffleIndex insts attempt to join
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; The partial group with the additional hoistable instructions will be hoisted in the next iteration
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; The pass is configured to run iteratively up to a maximum of the value specified by the WaveShuffleIndexSinkingMaxIterations regkey (default: 3)
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; Rerunning ensures that any potential hoistable instructions that were not added to a ShuffleGroup that are still profitable to merge will get merged eventually
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; ShuffleGroup consisting of %ws0 and %ws1 have established maximal InstChain, even though %ws1 and %ws2 could have formed a ShuffleGroup with a longer InstChain
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; ashr gets hoisted in next iteration when ShuffleGroup containing %ws1 and %ws2 gets constructed since %ws0 has no more suitable instructions in order to join the ShuffleGroup
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; Note: Hoisted instructions are to demonstrate functionality, InstCombine would reduce the shl by 2 and ashr by 1 to a single shl by 1
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; ------------------------------------------------
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define void @test_wave_shuffle_index_sinking(i32* %dst0, i32* %dst1, i32* %dst2, i32* %dst3, i32 %a, i32 %b, i32 %c) {
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; CHECK: [[HOISTED_I1:%.*]] = shl i32 %a, 2
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; CHECK: [[WS0:%.*]] = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 [[HOISTED_I1]], i32 0, i32 0)
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%ws0 = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 %a, i32 0, i32 0)
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; CHECK: [[ANCHOR1_HOISTED_I1:%.*]] = shl i32 %b, 2
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; CHECK-NEXT: [[ANCHOR1_WS0:%.*]] = add i32 [[WS0]], [[ANCHOR1_HOISTED_I1]]
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%add0 = add i32 %ws0, %b
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%shl0 = shl i32 %add0, 2
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; CHECK: store i32 [[ANCHOR1_WS0]], i32* %dst0
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store i32 %shl0, i32* %dst0
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; CHECK: [[HOISTED_I2:%.*]] = ashr i32 [[HOISTED_I1]], 1
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; CHECK: [[WS1:%.*]] = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 [[HOISTED_I2]], i32 1, i32 0)
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%ws1 = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 %a, i32 1, i32 0)
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; CHECK: [[ANCHOR1_HOISTED_I2:%.*]] = ashr i32 [[ANCHOR1_HOISTED_I1]], 1
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; CHECK: [[ANCHOR1_WS1:%.*]] = add i32 [[WS1]], [[ANCHOR1_HOISTED_I2]]
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%add1 = add i32 %ws1, %b
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%shl1 = shl i32 %add1, 2
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; CHECK: [[ANCHOR2_HOISTED_I2:%.*]] = ashr i32 %c, 1
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; CHECK-NEXT: [[ANCHOR2_WS1:%.*]] = mul i32 [[ANCHOR1_WS1]], [[ANCHOR2_HOISTED_I2]]
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%mul1 = mul i32 %shl1, %c
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%ashr1 = ashr i32 %mul1, 1
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; CHECK: store i32 [[ANCHOR2_WS1]], i32* %dst1
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store i32 %ashr1, i32* %dst1
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; CHECK: [[WS2:%.*]] = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 [[HOISTED_I2]], i32 2, i32 0)
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%ws2 = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 %a, i32 2, i32 0)
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; CHECK: [[ANCHOR1_WS2:%.*]] = add i32 [[WS2]], [[ANCHOR1_HOISTED_I2]]
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%add2 = add i32 %ws2, %b
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%shl2 = shl i32 %add2, 2
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; CHECK: [[ANCHOR2_WS2:%.*]] = mul i32 [[ANCHOR1_WS2]], [[ANCHOR2_HOISTED_I2]]
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%mul2 = mul i32 %shl2, %c
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%ashr2 = ashr i32 %mul2, 1
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; CHECK: store i32 [[ANCHOR2_WS2]], i32* %dst2
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store i32 %ashr2, i32* %dst2
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; CHECK: [[WS3:%.*]] = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 [[HOISTED_I2]], i32 3, i32 0)
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%ws3 = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 %a, i32 3, i32 0)
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; CHECK: [[ANCHOR1_WS3:%.*]] = add i32 [[WS3]], [[ANCHOR1_HOISTED_I2]]
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%add3 = add i32 %ws3, %b
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%shl3 = shl i32 %add3, 2
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; CHECK: [[ANCHOR2_WS3:%.*]] = mul i32 [[ANCHOR1_WS3]], [[ANCHOR2_HOISTED_I2]]
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%mul3 = mul i32 %shl3, %c
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%ashr3 = ashr i32 %mul3, 1
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; CHECK: store i32 [[ANCHOR2_WS3]], i32* %dst3
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store i32 %ashr3, i32* %dst3
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ret void
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}
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; Function Attrs: convergent nounwind readnone
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declare i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32, i32, i32) #0
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attributes #0 = { convergent nounwind readnone }

‎IGC/Compiler/tests/WaveShuffleIndexSinking/two-iterations-trim.ll‎

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;=========================== begin_copyright_notice ============================
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;
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; Copyright (C) 2024 Intel Corporation
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;
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; SPDX-License-Identifier: MIT
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;
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;============================ end_copyright_notice =============================
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; RUN: igc_opt -igc-wave-shuffle-index-sinking -S < %s | FileCheck %s
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; ------------------------------------------------
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; WaveShuffleIndexSinking
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;
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; An initial ShuffleGroup's InstChain may get reduced to encompass a wider number of WaveShuffleIndex that have fewer similar instructions
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; The pass is configured to run iteratively up to a maximum of the value specified by the WaveShuffleIndexSinkingMaxIterations regkey (default: 3)
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; Rerunning ensures that any potential hoistable instructions that were kicked out of a ShuffleGroup that are still profitable to merge will get merged eventually
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; ShuffleGroup consisting of %ws0, %ws1, and %ws2 gets trimmed in first iteration in order to accommodate %ws3
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; ashr gets hoisted in next iteration when ShuffleGroup (%ws0, %ws1, %ws2) gets reconstructed and %ws3 has no more suitable instructions in order to join the ShuffleGroup
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; Note: Hoisted instructions are to demonstrate functionality, InstCombine would reduce the shl by 2 and ashr by 1 to a single shl by 1
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; ------------------------------------------------
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define void @test_wave_shuffle_index_sinking(i32* %dst0, i32* %dst1, i32* %dst2, i32* %dst3, i32 %a, i32 %b, i32 %c) {
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; CHECK: [[HOISTED_I1:%.*]] = shl i32 %a, 2
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; CHECK: [[HOISTED_I2:%.*]] = ashr i32 [[HOISTED_I1]], 1
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; CHECK: [[WS0:%.*]] = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 [[HOISTED_I2]], i32 0, i32 0)
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%ws0 = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 %a, i32 0, i32 0)
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; CHECK: [[ANCHOR1_HOISTED_I1:%.*]] = shl i32 %b, 2
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; CHECK: [[ANCHOR1_HOISTED_I2:%.*]] = ashr i32 [[ANCHOR1_HOISTED_I1]], 1
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; CHECK-NEXT: [[ANCHOR1_WS0:%.*]] = add i32 [[WS0]], [[ANCHOR1_HOISTED_I2]]
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%add0 = add i32 %ws0, %b
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%shl0 = shl i32 %add0, 2
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; CHECK: [[ANCHOR2_HOISTED_I2:%.*]] = ashr i32 %c, 1
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; CHECK-NEXT: [[ANCHOR2_WS0:%.*]] = mul i32 [[ANCHOR1_WS0]], [[ANCHOR2_HOISTED_I2]]
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%mul0 = mul i32 %shl0, %c
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%ashr0 = ashr i32 %mul0, 1
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; CHECK: store i32 [[ANCHOR2_WS0]], i32* %dst0
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store i32 %ashr0, i32* %dst0
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; CHECK: [[WS1:%.*]] = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 [[HOISTED_I2]], i32 1, i32 0)
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%ws1 = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 %a, i32 1, i32 0)
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; CHECK: [[ANCHOR1_WS1:%.*]] = add i32 [[WS1]], [[ANCHOR1_HOISTED_I2]]
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%add1 = add i32 %ws1, %b
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%shl1 = shl i32 %add1, 2
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; CHECK: [[ANCHOR2_WS1:%.*]] = mul i32 [[ANCHOR1_WS1]], [[ANCHOR2_HOISTED_I2]]
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%mul1 = mul i32 %shl1, %c
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%ashr1 = ashr i32 %mul1, 1
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; CHECK: store i32 [[ANCHOR2_WS1]], i32* %dst1
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store i32 %ashr1, i32* %dst1
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; CHECK: [[WS2:%.*]] = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 [[HOISTED_I2]], i32 2, i32 0)
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%ws2 = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 %a, i32 2, i32 0)
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; CHECK: [[ANCHOR1_WS2:%.*]] = add i32 [[WS2]], [[ANCHOR1_HOISTED_I2]]
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%add2 = add i32 %ws2, %b
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%shl2 = shl i32 %add2, 2
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; CHECK: [[ANCHOR2_WS2:%.*]] = mul i32 [[ANCHOR1_WS2]], [[ANCHOR2_HOISTED_I2]]
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%mul2 = mul i32 %shl2, %c
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%ashr2 = ashr i32 %mul2, 1
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; CHECK: store i32 [[ANCHOR2_WS2]], i32* %dst2
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store i32 %ashr2, i32* %dst2
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; CHECK: [[WS3:%.*]] = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 [[HOISTED_I1]], i32 3, i32 0)
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%ws3 = call i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32 %a, i32 3, i32 0)
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; CHECK: [[ANCHOR1_WS3:%.*]] = add i32 [[WS3]], [[ANCHOR1_HOISTED_I1]]
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%add3 = add i32 %ws3, %b
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%shl3 = shl i32 %add3, 2
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; CHECK: store i32 [[ANCHOR1_WS3]], i32* %dst3
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store i32 %shl3, i32* %dst3
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ret void
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}
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; Function Attrs: convergent nounwind readnone
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declare i32 @llvm.genx.GenISA.WaveShuffleIndex.i32(i32, i32, i32) #0
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attributes #0 = { convergent nounwind readnone }

‎IGC/GenISAIntrinsics/GenIntrinsicInst.h‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1205,6 +1205,25 @@ class WavePrefixIntrinsic : public GenIntrinsicInst
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}
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};
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class WaveShuffleIndexIntrinsic : public GenIntrinsicInst
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{
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public:
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Value* getSrc() const { return getOperand( 0 ); }
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Value* getChannel() const { return getOperand( 1 ); }
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void setSrc( Value* src ) { setOperand( 0, src ); }
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// Methods for support type inquiry through isa, cast, and dyn_cast:
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static inline bool classof( const GenIntrinsicInst* I )
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{
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return I->getIntrinsicID() == GenISAIntrinsic::GenISA_WaveShuffleIndex;
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}
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static inline bool classof( const Value* V )
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{
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return isa<GenIntrinsicInst>( V ) && classof( cast<GenIntrinsicInst>( V ) );
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}
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};
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class QuadPrefixIntrinsic : public GenIntrinsicInst
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{
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public:

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