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target/loongarch/gdbstub: Add vector registers support
GDB already support LoongArch vector extension[1], QEMU gdb adds LoongArch vector registers support, so that users can use 'info all-registers' to get all vector registers values. [1]: https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=1e9569f383a3d5a88ee07d0c2401bd95613c222e Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewd-by: Bibo Mao <maobibo@loongson.cn> Message-Id: <20240711024454.3075183-1-gaosong@loongson.cn>
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‎configs/targets/loongarch64-linux-user.mak‎

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# Default configuration for loongarch64-linux-user
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TARGET_ARCH=loongarch64
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TARGET_BASE_ARCH=loongarch
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TARGET_XML_FILES=gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml
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TARGET_XML_FILES=gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml gdb-xml/loongarch-lsx.xml gdb-xml/loongarch-lasx.xml

‎configs/targets/loongarch64-softmmu.mak‎

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@@ -2,6 +2,6 @@ TARGET_ARCH=loongarch64
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TARGET_BASE_ARCH=loongarch
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TARGET_KVM_HAVE_GUEST_DEBUG=y
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TARGET_SUPPORTS_MTTCG=y
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TARGET_XML_FILES= gdb-xml/loongarch-base32.xml gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml
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TARGET_XML_FILES= gdb-xml/loongarch-base32.xml gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml gdb-xml/loongarch-lsx.xml gdb-xml/loongarch-lasx.xml
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# all boards require libfdt
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TARGET_NEED_FDT=y

‎gdb-xml/loongarch-lasx.xml‎

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<?xml version="1.0"?>
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<!-- Copyright (C) 2022-2024 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved. -->
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<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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<feature name="org.gnu.gdb.loongarch.lasx">
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<vector id="v8f32" type="ieee_single" count="8"/>
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<vector id="v4f64" type="ieee_double" count="4"/>
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<vector id="v32i8" type="int8" count="32"/>
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<vector id="v16i16" type="int16" count="16"/>
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<vector id="v8i32" type="int32" count="8"/>
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<vector id="v4i64" type="int64" count="4"/>
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<vector id="v2ui128" type="uint128" count="2"/>
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<union id="lasxv">
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<field name="v8_float" type="v8f32"/>
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<field name="v4_double" type="v4f64"/>
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<field name="v32_int8" type="v32i8"/>
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<field name="v16_int16" type="v16i16"/>
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<field name="v8_int32" type="v8i32"/>
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<field name="v4_int64" type="v4i64"/>
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<field name="v2_uint128" type="v2ui128"/>
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</union>
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<reg name="xr0" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr1" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr2" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr3" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr4" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr5" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr6" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr7" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr8" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr9" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr10" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr11" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr12" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr13" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr14" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr15" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr16" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr17" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr18" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr19" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr20" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr21" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr22" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr23" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr24" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr25" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr26" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr27" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr28" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr29" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr30" bitsize="256" type="lasxv" group="lasx"/>
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<reg name="xr31" bitsize="256" type="lasxv" group="lasx"/>
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</feature>

‎gdb-xml/loongarch-lsx.xml‎

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<?xml version="1.0"?>
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<!-- Copyright (C) 2022-2024 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved. -->
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<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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<feature name="org.gnu.gdb.loongarch.lsx">
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<vector id="v4f32" type="ieee_single" count="4"/>
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<vector id="v2f64" type="ieee_double" count="2"/>
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<vector id="v16i8" type="int8" count="16"/>
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<vector id="v8i16" type="int16" count="8"/>
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<vector id="v4i32" type="int32" count="4"/>
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<vector id="v2i64" type="int64" count="2"/>
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<union id="lsxv">
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<field name="v4_float" type="v4f32"/>
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<field name="v2_double" type="v2f64"/>
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<field name="v16_int8" type="v16i8"/>
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<field name="v8_int16" type="v8i16"/>
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<field name="v4_int32" type="v4i32"/>
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<field name="v2_int64" type="v2i64"/>
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<field name="uint128" type="uint128"/>
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</union>
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<reg name="vr0" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr1" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr2" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr3" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr4" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr5" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr6" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr7" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr8" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr9" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr10" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr11" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr12" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr13" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr14" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr15" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr16" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr17" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr18" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr19" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr20" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr21" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr22" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr23" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr26" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr25" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr26" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr27" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr28" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr29" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr30" bitsize="128" type="lsxv" group="lsx"/>
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<reg name="vr31" bitsize="128" type="lsxv" group="lsx"/>
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</feature>

‎target/loongarch/gdbstub.c‎

Lines changed: 71 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -116,8 +116,77 @@ static int loongarch_gdb_set_fpu(CPUState *cs, uint8_t *mem_buf, int n)
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return length;
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}
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#define VREG_NUM 32
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#define REG64_LEN 64
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static int loongarch_gdb_get_vec(CPUState *cs, GByteArray *mem_buf, int n, int vl)
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{
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LoongArchCPU *cpu = LOONGARCH_CPU(cs);
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CPULoongArchState *env = &cpu->env;
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int i, length = 0;
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if (0 <= n && n < VREG_NUM) {
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for (i = 0; i < vl / REG64_LEN; i++) {
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length += gdb_get_reg64(mem_buf, env->fpr[n].vreg.D(i));
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}
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}
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return length;
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}
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static int loongarch_gdb_set_vec(CPUState *cs, uint8_t *mem_buf, int n, int vl)
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{
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LoongArchCPU *cpu = LOONGARCH_CPU(cs);
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CPULoongArchState *env = &cpu->env;
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int i, length = 0;
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if (0 <= n && n < VREG_NUM) {
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for (i = 0; i < vl / REG64_LEN; i++) {
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env->fpr[n].vreg.D(i) = ldq_le_p(mem_buf + 8 * i);
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length += 8;
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}
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}
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return length;
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}
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static int loongarch_gdb_get_lsx(CPUState *cs, GByteArray *mem_buf, int n)
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{
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return loongarch_gdb_get_vec(cs, mem_buf, n, LSX_LEN);
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}
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static int loongarch_gdb_set_lsx(CPUState *cs, uint8_t *mem_buf, int n)
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{
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return loongarch_gdb_set_vec(cs, mem_buf, n, LSX_LEN);
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}
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static int loongarch_gdb_get_lasx(CPUState *cs, GByteArray *mem_buf, int n)
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{
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return loongarch_gdb_get_vec(cs, mem_buf, n, LASX_LEN);
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}
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static int loongarch_gdb_set_lasx(CPUState *cs, uint8_t *mem_buf, int n)
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{
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return loongarch_gdb_set_vec(cs, mem_buf, n, LASX_LEN);
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}
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void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs)
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{
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gdb_register_coprocessor(cs, loongarch_gdb_get_fpu, loongarch_gdb_set_fpu,
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gdb_find_static_feature("loongarch-fpu.xml"), 0);
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LoongArchCPU *cpu = LOONGARCH_CPU(cs);
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CPULoongArchState *env = &cpu->env;
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if (FIELD_EX32(env->cpucfg[2], CPUCFG2, FP)) {
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gdb_register_coprocessor(cs, loongarch_gdb_get_fpu, loongarch_gdb_set_fpu,
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gdb_find_static_feature("loongarch-fpu.xml"), 0);
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}
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if (FIELD_EX32(env->cpucfg[2], CPUCFG2, LSX)) {
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gdb_register_coprocessor(cs, loongarch_gdb_get_lsx, loongarch_gdb_set_lsx,
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gdb_find_static_feature("loongarch-lsx.xml"), 0);
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}
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if (FIELD_EX32(env->cpucfg[2], CPUCFG2, LASX)) {
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gdb_register_coprocessor(cs, loongarch_gdb_get_lasx, loongarch_gdb_set_lasx,
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gdb_find_static_feature("loongarch-lasx.xml"), 0);
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}
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}

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