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Merge tag 'pull-riscv-to-apply-20240718-1' of https://github.com/alistair23/qemu into staging
RISC-V PR for 9.1 * Support the zimop, zcmop, zama16b and zabha extensions * Validate the mode when setting vstvec CSR * Add decode support for Zawrs extension * Update the KVM regs to Linux 6.10-rc5 * Add smcntrpmf extension support * Raise an exception when CSRRS/CSRRC writes a read-only CSR * Re-insert and deprecate 'riscv,delegate' in virt machine device tree * roms/opensbi: Update to v1.5 # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmaYeUcACgkQr3yVEwxT # gBMtdw//U2NbmnmECa0uXuE7fdFul0tUkl2oHb9Cr8g5Se5g/HVFqexAKOFZ8Lcm # DvTl94zJ2dms4RntcmJHwTIusa+oU6qqOekediotjgpeH4BHZNCOHe0E9hIAHn9F # uoJ1P186L7VeVr7OFAAgSCE7F6egCk7iC0h8L8/vuL4xcuyfbZ2r7ybiTl1+45N2 # YBBv5/00wsYnyMeqRYYtyqgX9QR017JRqNSfTJSbKxhQM/L1GA1xxisUvIGeyDqc # Pn8E3dMN6sscR6bPs4RP+SBi0JIlRCgth/jteSUkbYf42osw3/5sl4oK/e6Xiogo # SjELOF7QJNxE8H6EUIScDaCVB5ZhvELZcuOL2NRdUuVDkjhWXM633HwfEcXkZdFK # W/H9wOvNxPAJIOGXOpv10+MLmhdyIOZwE0uk6evHvdcTn3FP9DurdUCc1se0zKOA # Qg/H6usTbLGNQ7KKTNQ6GpQ6u89iE1CIyZqYVvB1YuF5t7vtAmxvNk3SVZ6aq3VL # lPJW2Zd1eO09Q+kRnBVDV7MV4OJrRNsU+ryd91NrSVo9aLADtyiNC28dCSkjU3Gn # 6YQZt65zHuhH5IBB/PGIPo7dLRT8KNWOiYVoy3c6p6DC6oXsKIibh0ue1nrVnnVQ # NRqyxPYaj6P8zzqwTk+iJj36UXZZVtqPIhtRu9MrO6Opl2AbsXI= # =pM6B # -----END PGP SIGNATURE----- # gpg: Signature made Thu 18 Jul 2024 12:09:11 PM AEST # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20240718-1' of https://github.com/alistair23/qemu: (30 commits) roms/opensbi: Update to v1.5 hw/riscv/virt.c: re-insert and deprecate 'riscv,delegate' target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR target/riscv: Expose the Smcntrpmf config target/riscv: Do not setup pmu timer if OF is disabled target/riscv: More accurately model priv mode filtering. target/riscv: Start counters from both mhpmcounter and mcountinhibit target/riscv: Enforce WARL behavior for scounteren/hcounteren target/riscv: Save counter values during countinhibit update target/riscv: Implement privilege mode filtering for cycle/instret target/riscv: Only set INH fields if priv mode is available target/riscv: Add cycle & instret privilege mode filtering support target/riscv: Add cycle & instret privilege mode filtering definitions target/riscv: Add cycle & instret privilege mode filtering properties target/riscv: Fix the predicate functions for mhpmeventhX CSRs target/riscv: Combine set_mode and set_virt functions. target/riscv/kvm: update KVM regs to Linux 6.10-rc5 disas/riscv: Add decode for Zawrs extension target/riscv: Validate the mode in write_vstvec disas/riscv: Support zabha disassemble ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2 parents d74ec4d + daff9f7 commit 0d9f101

29 files changed

+1246
-211
lines changed

‎disas/riscv.c‎

Lines changed: 187 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -906,6 +906,76 @@ typedef enum {
906906
rv_op_amocas_w = 875,
907907
rv_op_amocas_d = 876,
908908
rv_op_amocas_q = 877,
909+
rv_mop_r_0 = 878,
910+
rv_mop_r_1 = 879,
911+
rv_mop_r_2 = 880,
912+
rv_mop_r_3 = 881,
913+
rv_mop_r_4 = 882,
914+
rv_mop_r_5 = 883,
915+
rv_mop_r_6 = 884,
916+
rv_mop_r_7 = 885,
917+
rv_mop_r_8 = 886,
918+
rv_mop_r_9 = 887,
919+
rv_mop_r_10 = 888,
920+
rv_mop_r_11 = 889,
921+
rv_mop_r_12 = 890,
922+
rv_mop_r_13 = 891,
923+
rv_mop_r_14 = 892,
924+
rv_mop_r_15 = 893,
925+
rv_mop_r_16 = 894,
926+
rv_mop_r_17 = 895,
927+
rv_mop_r_18 = 896,
928+
rv_mop_r_19 = 897,
929+
rv_mop_r_20 = 898,
930+
rv_mop_r_21 = 899,
931+
rv_mop_r_22 = 900,
932+
rv_mop_r_23 = 901,
933+
rv_mop_r_24 = 902,
934+
rv_mop_r_25 = 903,
935+
rv_mop_r_26 = 904,
936+
rv_mop_r_27 = 905,
937+
rv_mop_r_28 = 906,
938+
rv_mop_r_29 = 907,
939+
rv_mop_r_30 = 908,
940+
rv_mop_r_31 = 909,
941+
rv_mop_rr_0 = 910,
942+
rv_mop_rr_1 = 911,
943+
rv_mop_rr_2 = 912,
944+
rv_mop_rr_3 = 913,
945+
rv_mop_rr_4 = 914,
946+
rv_mop_rr_5 = 915,
947+
rv_mop_rr_6 = 916,
948+
rv_mop_rr_7 = 917,
949+
rv_c_mop_1 = 918,
950+
rv_c_mop_3 = 919,
951+
rv_c_mop_5 = 920,
952+
rv_c_mop_7 = 921,
953+
rv_c_mop_9 = 922,
954+
rv_c_mop_11 = 923,
955+
rv_c_mop_13 = 924,
956+
rv_c_mop_15 = 925,
957+
rv_op_amoswap_b = 926,
958+
rv_op_amoadd_b = 927,
959+
rv_op_amoxor_b = 928,
960+
rv_op_amoor_b = 929,
961+
rv_op_amoand_b = 930,
962+
rv_op_amomin_b = 931,
963+
rv_op_amomax_b = 932,
964+
rv_op_amominu_b = 933,
965+
rv_op_amomaxu_b = 934,
966+
rv_op_amoswap_h = 935,
967+
rv_op_amoadd_h = 936,
968+
rv_op_amoxor_h = 937,
969+
rv_op_amoor_h = 938,
970+
rv_op_amoand_h = 939,
971+
rv_op_amomin_h = 940,
972+
rv_op_amomax_h = 941,
973+
rv_op_amominu_h = 942,
974+
rv_op_amomaxu_h = 943,
975+
rv_op_amocas_b = 944,
976+
rv_op_amocas_h = 945,
977+
rv_op_wrs_sto = 946,
978+
rv_op_wrs_nto = 947,
909979
} rv_op;
910980

911981
/* register names */
@@ -2096,6 +2166,76 @@ const rv_opcode_data rvi_opcode_data[] = {
20962166
{ "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
20972167
{ "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
20982168
{ "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2169+
{ "mop.r.0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2170+
{ "mop.r.1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2171+
{ "mop.r.2", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2172+
{ "mop.r.3", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2173+
{ "mop.r.4", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2174+
{ "mop.r.5", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2175+
{ "mop.r.6", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2176+
{ "mop.r.7", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2177+
{ "mop.r.8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2178+
{ "mop.r.9", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2179+
{ "mop.r.10", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2180+
{ "mop.r.11", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2181+
{ "mop.r.12", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2182+
{ "mop.r.13", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2183+
{ "mop.r.14", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2184+
{ "mop.r.15", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2185+
{ "mop.r.16", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2186+
{ "mop.r.17", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2187+
{ "mop.r.18", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2188+
{ "mop.r.19", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2189+
{ "mop.r.20", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2190+
{ "mop.r.21", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2191+
{ "mop.r.22", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2192+
{ "mop.r.23", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2193+
{ "mop.r.24", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2194+
{ "mop.r.25", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2195+
{ "mop.r.26", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2196+
{ "mop.r.27", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2197+
{ "mop.r.28", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2198+
{ "mop.r.29", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2199+
{ "mop.r.30", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2200+
{ "mop.r.31", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
2201+
{ "mop.rr.0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
2202+
{ "mop.rr.1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
2203+
{ "mop.rr.2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
2204+
{ "mop.rr.3", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
2205+
{ "mop.rr.4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
2206+
{ "mop.rr.5", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
2207+
{ "mop.rr.6", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
2208+
{ "mop.rr.7", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
2209+
{ "c.mop.1", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
2210+
{ "c.mop.3", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
2211+
{ "c.mop.5", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
2212+
{ "c.mop.7", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
2213+
{ "c.mop.9", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
2214+
{ "c.mop.11", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
2215+
{ "c.mop.13", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
2216+
{ "c.mop.15", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
2217+
{ "amoswap.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2218+
{ "amoadd.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2219+
{ "amoxor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2220+
{ "amoor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2221+
{ "amoand.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2222+
{ "amomin.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2223+
{ "amomax.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2224+
{ "amominu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2225+
{ "amomaxu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2226+
{ "amoswap.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2227+
{ "amoadd.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2228+
{ "amoxor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2229+
{ "amoor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2230+
{ "amoand.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2231+
{ "amomin.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2232+
{ "amomax.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2233+
{ "amominu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2234+
{ "amomaxu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2235+
{ "amocas.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2236+
{ "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
2237+
{ "wrs.sto", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
2238+
{ "wrs.nto", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
20992239
};
21002240

21012241
/* CSR names */
@@ -2452,6 +2592,13 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
24522592
break;
24532593
case 2: op = rv_op_c_li; break;
24542594
case 3:
2595+
if (dec->cfg->ext_zcmop) {
2596+
if ((((inst >> 2) & 0b111111) == 0b100000) &&
2597+
(((inst >> 11) & 0b11) == 0b0)) {
2598+
op = rv_c_mop_1 + ((inst >> 8) & 0b111);
2599+
break;
2600+
}
2601+
}
24552602
switch ((inst >> 7) & 0b11111) {
24562603
case 2: op = rv_op_c_addi16sp; break;
24572604
default: op = rv_op_c_lui; break;
@@ -2883,9 +3030,13 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
28833030
case 11:
28843031
switch (((inst >> 24) & 0b11111000) |
28853032
((inst >> 12) & 0b00000111)) {
3033+
case 0: op = rv_op_amoadd_b; break;
3034+
case 1: op = rv_op_amoadd_h; break;
28863035
case 2: op = rv_op_amoadd_w; break;
28873036
case 3: op = rv_op_amoadd_d; break;
28883037
case 4: op = rv_op_amoadd_q; break;
3038+
case 8: op = rv_op_amoswap_b; break;
3039+
case 9: op = rv_op_amoswap_h; break;
28893040
case 10: op = rv_op_amoswap_w; break;
28903041
case 11: op = rv_op_amoswap_d; break;
28913042
case 12: op = rv_op_amoswap_q; break;
@@ -2907,27 +3058,43 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
29073058
case 26: op = rv_op_sc_w; break;
29083059
case 27: op = rv_op_sc_d; break;
29093060
case 28: op = rv_op_sc_q; break;
3061+
case 32: op = rv_op_amoxor_b; break;
3062+
case 33: op = rv_op_amoxor_h; break;
29103063
case 34: op = rv_op_amoxor_w; break;
29113064
case 35: op = rv_op_amoxor_d; break;
29123065
case 36: op = rv_op_amoxor_q; break;
3066+
case 40: op = rv_op_amocas_b; break;
3067+
case 41: op = rv_op_amocas_h; break;
29133068
case 42: op = rv_op_amocas_w; break;
29143069
case 43: op = rv_op_amocas_d; break;
29153070
case 44: op = rv_op_amocas_q; break;
3071+
case 64: op = rv_op_amoor_b; break;
3072+
case 65: op = rv_op_amoor_h; break;
29163073
case 66: op = rv_op_amoor_w; break;
29173074
case 67: op = rv_op_amoor_d; break;
29183075
case 68: op = rv_op_amoor_q; break;
3076+
case 96: op = rv_op_amoand_b; break;
3077+
case 97: op = rv_op_amoand_h; break;
29193078
case 98: op = rv_op_amoand_w; break;
29203079
case 99: op = rv_op_amoand_d; break;
29213080
case 100: op = rv_op_amoand_q; break;
3081+
case 128: op = rv_op_amomin_b; break;
3082+
case 129: op = rv_op_amomin_h; break;
29223083
case 130: op = rv_op_amomin_w; break;
29233084
case 131: op = rv_op_amomin_d; break;
29243085
case 132: op = rv_op_amomin_q; break;
3086+
case 160: op = rv_op_amomax_b; break;
3087+
case 161: op = rv_op_amomax_h; break;
29253088
case 162: op = rv_op_amomax_w; break;
29263089
case 163: op = rv_op_amomax_d; break;
29273090
case 164: op = rv_op_amomax_q; break;
3091+
case 192: op = rv_op_amominu_b; break;
3092+
case 193: op = rv_op_amominu_h; break;
29283093
case 194: op = rv_op_amominu_w; break;
29293094
case 195: op = rv_op_amominu_d; break;
29303095
case 196: op = rv_op_amominu_q; break;
3096+
case 224: op = rv_op_amomaxu_b; break;
3097+
case 225: op = rv_op_amomaxu_h; break;
29313098
case 226: op = rv_op_amomaxu_w; break;
29323099
case 227: op = rv_op_amomaxu_d; break;
29333100
case 228: op = rv_op_amomaxu_q; break;
@@ -3817,6 +3984,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
38173984
case 0: op = rv_op_ecall; break;
38183985
case 32: op = rv_op_ebreak; break;
38193986
case 64: op = rv_op_uret; break;
3987+
case 416: op = rv_op_wrs_nto; break;
3988+
case 928: op = rv_op_wrs_sto; break;
38203989
}
38213990
break;
38223991
case 256:
@@ -3855,6 +4024,24 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
38554024
case 1: op = rv_op_csrrw; break;
38564025
case 2: op = rv_op_csrrs; break;
38574026
case 3: op = rv_op_csrrc; break;
4027+
case 4:
4028+
if (dec->cfg->ext_zimop) {
4029+
int imm_mop5, imm_mop3;
4030+
if ((extract32(inst, 22, 10) & 0b1011001111)
4031+
== 0b1000000111) {
4032+
imm_mop5 = deposit32(deposit32(extract32(inst, 20, 2),
4033+
2, 2,
4034+
extract32(inst, 26, 2)),
4035+
4, 1, extract32(inst, 30, 1));
4036+
op = rv_mop_r_0 + imm_mop5;
4037+
} else if ((extract32(inst, 25, 7) & 0b1011001)
4038+
== 0b1000001) {
4039+
imm_mop3 = deposit32(extract32(inst, 26, 2),
4040+
2, 1, extract32(inst, 30, 1));
4041+
op = rv_mop_rr_0 + imm_mop3;
4042+
}
4043+
}
4044+
break;
38584045
case 5: op = rv_op_csrrwi; break;
38594046
case 6: op = rv_op_csrrsi; break;
38604047
case 7: op = rv_op_csrrci; break;

‎docs/about/deprecated.rst‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -479,6 +479,17 @@ versions, aliases will point to newer CPU model versions
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depending on the machine type, so management software must
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resolve CPU model aliases before starting a virtual machine.
481481

482+
RISC-V "virt" board "riscv,delegate" DT property (since 9.1)
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''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
484+
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The "riscv,delegate" DT property was added in QEMU 7.0 as part of
486+
the AIA APLIC support. The property changed name during the review
487+
process in Linux and the correct name ended up being
488+
"riscv,delegation". Changing the DT property name will break all
489+
available firmwares that are using the current (wrong) name. The
490+
property is kept as is in 9.1, together with "riscv,delegation", to
491+
give more time for firmware developers to change their code.
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482493
Migration
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---------
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‎hw/riscv/virt.c‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -651,6 +651,15 @@ static void create_fdt_one_aplic(RISCVVirtState *s, int socket,
651651
qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegation",
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aplic_child_phandle, 0x1,
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VIRT_IRQCHIP_NUM_SOURCES);
654+
/*
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* DEPRECATED_9.1: Compat property kept temporarily
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* to allow old firmwares to work with AIA. Do *not*
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* use 'riscv,delegate' in new code: use
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* 'riscv,delegation' instead.
659+
*/
660+
qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate",
661+
aplic_child_phandle, 0x1,
662+
VIRT_IRQCHIP_NUM_SOURCES);
654663
}
655664

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riscv_socket_fdt_write_id(ms, aplic_name, socket);

‎pc-bios/opensbi-riscv32-generic-fw_dynamic.bin‎

896 Bytes
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‎pc-bios/opensbi-riscv64-generic-fw_dynamic.bin‎

1.66 KB
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‎roms/opensbi‎

Submodule opensbi updated from a2b255b to 455de67

‎target/riscv/cpu.c‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -113,10 +113,13 @@ const RISCVIsaExtData isa_edata_arr[] = {
113113
ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl),
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ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
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ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm),
116+
ISA_EXT_DATA_ENTRY(zimop, PRIV_VERSION_1_13_0, ext_zimop),
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ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
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ISA_EXT_DATA_ENTRY(za64rs, PRIV_VERSION_1_12_0, has_priv_1_11),
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ISA_EXT_DATA_ENTRY(zaamo, PRIV_VERSION_1_12_0, ext_zaamo),
120+
ISA_EXT_DATA_ENTRY(zabha, PRIV_VERSION_1_13_0, ext_zabha),
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ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas),
122+
ISA_EXT_DATA_ENTRY(zama16b, PRIV_VERSION_1_13_0, ext_zama16b),
120123
ISA_EXT_DATA_ENTRY(zalrsc, PRIV_VERSION_1_12_0, ext_zalrsc),
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ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
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ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa),
@@ -130,6 +133,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
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ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf),
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ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd),
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ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce),
136+
ISA_EXT_DATA_ENTRY(zcmop, PRIV_VERSION_1_13_0, ext_zcmop),
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ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp),
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ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt),
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ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba),
@@ -178,6 +182,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
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ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
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ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
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ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
185+
ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
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ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
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ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
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ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
@@ -1467,11 +1472,16 @@ const char *riscv_get_misa_ext_description(uint32_t bit)
14671472
const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
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/* Defaults for standard extensions */
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MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
1475+
MULTI_EXT_CFG_BOOL("smcntrpmf", ext_smcntrpmf, false),
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MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true),
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MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true),
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MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
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MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true),
1480+
MULTI_EXT_CFG_BOOL("zimop", ext_zimop, false),
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MULTI_EXT_CFG_BOOL("zcmop", ext_zcmop, false),
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MULTI_EXT_CFG_BOOL("zacas", ext_zacas, false),
1483+
MULTI_EXT_CFG_BOOL("zama16b", ext_zama16b, false),
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MULTI_EXT_CFG_BOOL("zabha", ext_zabha, false),
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MULTI_EXT_CFG_BOOL("zaamo", ext_zaamo, false),
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MULTI_EXT_CFG_BOOL("zalrsc", ext_zalrsc, false),
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MULTI_EXT_CFG_BOOL("zawrs", ext_zawrs, true),

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